ATmega169P
Figure 24-4. General Port Pin Schematic Diagram
See Boundary-scan
Description for Details!
PUExn
PUD
Q
D
DDxn
Q CLR
WDx
RDx
RESET
OCxn
Pxn
1
0
Q
D
PORTxn
ODxn
IDxn
Q CLR
RESET
WPx
WRx
SLEEP
RRx
SYNCHRONIZER
RPx
D
Q
D
L
Q
Q
PINxn
Q
CLK I/O
PUD:
PULLUP DISABLE
WDx:
RDx:
WRx:
RRx:
RPx:
WRITE DDRx
READ DDRx
WRITE PORTx
PUExn:
OCxn:
ODxn:
IDxn:
PULLUP ENABLE for pin Pxn
OUTPUT CONTROL for pin Pxn
OUTPUT DATA to pin Pxn
INPUT DATA from pin Pxn
SLEEP CONTROL
READ PORTx REGISTER
READ PORTx PIN
WRITE PINx REGISTER
I/O CLOCK
WPx:
CLK I/O
SLEEP:
:
263
8018A–AVR–03/06