(TEMP). This temporary register is shared by all the other 16-bit registers. See “Accessing 16-bit
Registers” on page 138.
Modifying the counter (TCNTn) while the counter is running introduces a risk of missing a com-
pare match between TCNTn and one of the OCRnx Registers.
Writing to the TCNTn Register blocks (removes) the compare match on the following timer clock
for all compare units.
17.11.17 OCR1AH and OCR1AL – Output Compare Register 1 A
Bit
7
6
5
4
3
2
1
0
(0x89)
OCR1A[15:8]
OCR1A[7:0]
OCR1AH
OCR1AL
(0x88)
Read/Write
Initial Value
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
17.11.18 OCR1BH and OCR1BL – Output Compare Register 1 B
Bit
7
6
5
4
3
2
1
0
(0x8B)
OCR1B[15:8]
OCR1B[7:0]
OCR1BH
OCR1BL
(0x8A)
Read/Write
Initial Value
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
17.11.19 OCR1CH and OCR1CL – Output Compare Register 1 C
Bit
7
6
5
4
3
2
1
0
(0x8D)
OCR1C[15:8]
OCR1C[7:0]
OCR1CH
OCR1CL
(0x8C)
Read/Write
Initial Value
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
17.11.20 OCR3AH and OCR3AL – Output Compare Register 3 A
Bit
7
6
5
4
3
2
1
0
(0x99)
OCR3A[15:8]
OCR3A[7:0]
OCR3AH
OCR3AL
(0x98)
Read/Write
Initial Value
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
17.11.21 OCR3BH and OCR3BL – Output Compare Register 3 B
Bit
7
6
5
4
3
2
1
0
(0x9B)
OCR3B[15:8]
OCR3B[7:0]
OCR3BH
OCR3BL
(0x9A)
Read/Write
Initial Value
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
17.11.22 OCR3CH and OCR3CL – Output Compare Register 3 C
Bit
7
6
5
4
3
2
1
0
(0x9D)
OCR3C[15:8]
OCR3C[7:0]
OCR3CH
OCR3CL
(0x9C)
Read/Write
Initial Value
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
164
ATmega640/1280/1281/2560/2561
2549L–AVR–08/07
ATMEL [ ATMEL ]
