17.11.36 TIMSK5 – Timer/Counter 5 Interrupt Mask Register
Bit
7
–
6
–
5
ICIE5
R/W
0
4
–
3
OCIE5C
R/W
0
2
OCIE5B
R/W
0
1
OCIE5A
R/W
0
0
TOIE5
R/W
0
(0x73)
TIMSK5
Read/Write
Initial Value
R
0
R
0
R
0
• Bit 5 – ICIEn: Timer/Countern, Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Countern Input Capture interrupt is enabled. The corresponding Interrupt
Vector (See “Interrupts” on page 105.) is executed when the ICFn Flag, located in TIFRn, is set.
• Bit 3 – OCIEnC: Timer/Countern, Output Compare C Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Countern Output Compare C Match interrupt is enabled. The corresponding
Interrupt Vector (See “Interrupts” on page 105.) is executed when the OCFnC Flag, located in
TIFRn, is set.
• Bit 2 – OCIEnB: Timer/Countern, Output Compare B Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Countern Output Compare B Match interrupt is enabled. The corresponding
Interrupt Vector (See “Interrupts” on page 105.) is executed when the OCFnB Flag, located in
TIFRn, is set.
• Bit 1 – OCIEnA: Timer/Countern, Output Compare A Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Countern Output Compare A Match interrupt is enabled. The corresponding
Interrupt Vector (See “Interrupts” on page 105.) is executed when the OCFnA Flag, located in
TIFRn, is set.
• Bit 0 – TOIEn: Timer/Countern, Overflow Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Countern Overflow interrupt is enabled. The corresponding Interrupt Vector
(See “Interrupts” on page 105.) is executed when the TOVn Flag, located in TIFRn, is set.
17.11.37 TIFR1 – Timer/Counter1 Interrupt Flag Register
Bit
0x16 (0x36)
7
6
5
4
–
3
OCF1C
R/W
0
2
OCF1B
R/W
0
1
OCF1A
R/W
0
0
TOV1
R/W
0
–
–
ICF1
R/W
0
TIFR1
Read/Write
R
0
R
0
R
0
Initial Value
17.11.38 TIFR3 – Timer/Counter3 Interrupt Flag Register
Bit
7
–
6
–
5
4
–
3
OCF3C
R/W
0
2
OCF3B
R/W
0
1
OCF3A
R/W
0
0
TOV3
R/W
0
0x18 (0x38)
Read/Write
Initial Value
ICF3
R/W
0
TIFR3
R
0
R
0
R
0
168
ATmega640/1280/1281/2560/2561
2549L–AVR–08/07
ATMEL [ ATMEL ]
