17.11.24 OCR4BH and OCR4BL – Output Compare Register 4 B
Bit
7
6
5
4
3
2
1
0
(0xAA)
OCR4B[15:8]
OCR4B[7:0]
OCR4BH
OCR4BL
(0xAB)
Read/Write
Initial Value
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
17.11.25 OCR4CH and OCR4CL –Output Compare Register 4 C
Bit
7
6
5
4
3
2
1
0
(0xAD)
OCR4C[15:8]
OCR4C[7:0]
OCR4CH
OCR4CL
(0xAC)
Read/Write
Initial Value
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
17.11.26 OCR5AH and OCR5AL – Output Compare Register 5 A
Bit
7
6
5
4
3
2
1
0
(0x129)
(0x128)
Read/Write
Initial Value
OCR5A[15:8]
OCR5A[7:0]
OCR5AH
OCR5AL
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
17.11.27 OCR5BH and OCR5BL – Output Compare Register 5 B
Bit
7
6
5
4
3
2
1
0
(0x12B)
(0x12A)
Read/Write
Initial Value
OCR5B[15:8]
OCR5B[7:0]
OCR5BH
OCR5BL
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
17.11.28 OCR5CH and OCR5CL –Output Compare Register 5 C
Bit
7
6
5
4
3
2
1
0
(0x12D)
(0x12C)
Read/Write
Initial Value
OCR5C[15:8]
OCR5C[7:0]
OCR5CH
OCR5CL
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
The Output Compare Registers contain a 16-bit value that is continuously compared with the
counter value (TCNTn). A match can be used to generate an Output Compare interrupt, or to
generate a waveform output on the OCnx pin.
The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are
written simultaneously when the CPU writes to these registers, the access is performed using an
8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other
16-bit registers. See “Accessing 16-bit Registers” on page 138.
17.11.29 ICR1H and ICR1L – Input Capture Register 1
Bit
7
6
5
4
3
2
1
0
(0x87)
ICR1[15:8]
ICR1[7:0]
ICR1H
ICR1L
(0x86)
Read/Write
Initial Value
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
166
ATmega640/1280/1281/2560/2561
2549L–AVR–08/07
ATMEL [ ATMEL ]
