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ATMEGA2560-16AU-SL383 参数 Datasheet PDF下载

ATMEGA2560-16AU-SL383图片预览
型号: ATMEGA2560-16AU-SL383
PDF下载: 下载PDF文件 查看货源
内容描述: [Microcontroller, 8-Bit, FLASH, AVR RISC CPU, 16MHz, CMOS, PQFP100, 14 X 14 MM, 1 MM HEIGHT, 0.50 MM PITCH, GREEN, PLASTIC, MS-026AED, TQFP-100]
分类和应用: 时钟微控制器
文件页数/大小: 448 页 / 7518 K
品牌: ATMEL [ ATMEL ]
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Table 17-3. Compare Output Mode, non-PWM  
COMnA1  
COMnB1  
COMnC1  
COMnA0  
COMnB0  
COMnC0  
Description  
0
0
1
1
0
1
0
1
Normal port operation, OCnA/OCnB/OCnC disconnected.  
Toggle OCnA/OCnB/OCnC on compare match.  
Clear OCnA/OCnB/OCnC on compare match (set output to low level).  
Set OCnA/OCnB/OCnC on compare match (set output to high level).  
Table 17-4 shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to the fast  
PWM mode.  
Table 17-4. Compare Output Mode, Fast PWM  
COMnA1  
COMnB1  
COMnC1  
COMnA0  
COMnB0  
COMnC0  
Description  
0
0
Normal port operation, OCnA/OCnB/OCnC disconnected.  
WGM13:0 = 14 or 15: Toggle OC1A on Compare Match, OC1B and OC1C  
disconnected (normal port operation). For all other WGM1 settings, normal  
port operation, OC1A/OC1B/OC1C disconnected.  
0
1
Clear OCnA/OCnB/OCnC on compare match, set OCnA/OCnB/OCnC at  
BOTTOM (non-inverting mode).  
1
1
0
1
Set OCnA/OCnB/OCnC on compare match, clear OCnA/OCnB/OCnC at  
BOTTOM (inverting mode).  
Note:  
A special case occurs when OCRnA/OCRnB/OCRnC equals TOP and  
COMnA1/COMnB1/COMnC1 is set. In this case the compare match is ignored, but the set or clear  
is done at BOTTOM. See “Fast PWM Mode” on page 150. for more details.  
Table 17-5 shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to the phase  
correct and frequency correct PWM mode.  
Table 17-5. Compare Output Mode, Phase Correct and Phase and Frequency Correct PWM  
COMnA1  
COMnB1  
COMnC1  
COMnA0  
COMnB0  
COMnC0  
Description  
0
0
Normal port operation, OCnA/OCnB/OCnC disconnected.  
WGM13:0 =9 or 11: Toggle OC1A on Compare Match, OC1B and OC1C  
disconnected (normal port operation). For all other WGM1 settings, normal  
port operation, OC1A/OC1B/OC1C disconnected.  
0
1
Clear OCnA/OCnB/OCnC on compare match when up-counting. Set  
OCnA/OCnB/OCnC on compare match when downcounting.  
1
1
0
1
Set OCnA/OCnB/OCnC on compare match when up-counting. Clear  
OCnA/OCnB/OCnC on compare match when downcounting.  
Note:  
A special case occurs when OCRnA/OCRnB/OCRnC equals TOP and  
COMnA1/COMnB1//COMnC1 is set. See “Phase Correct PWM Mode” on page 152. for more  
details.  
160  
ATmega640/1280/1281/2560/2561  
2549L–AVR–08/07  
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