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AT90PWM3B-16SU 参数 Datasheet PDF下载

AT90PWM3B-16SU图片预览
型号: AT90PWM3B-16SU
PDF下载: 下载PDF文件 查看货源
内容描述: 8位微控制器具有8K字节的系统内可编程闪存 [8-bit Microcontroller with 8K Bytes In-System Programmable Flash]
分类和应用: 闪存微控制器
文件页数/大小: 361 页 / 6022 K
品牌: ATMEL [ ATMEL ]
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AT90PWM2/3/2B/3B  
19.3.3.1  
Manchester frame  
The USART supports Manchester encoded frames with the following characteristics:  
One start bit Manchester encoded (logical ‘1’)  
5, 6, 7, 8, 9, 13, 14,15,16,17 data bits in transmission or reception (MSB or LSB first)  
The number of data bit in a frame is independently configurable in reception and  
transmission mode.  
One or Two stop bits (level encoded)  
Figure 19-3. Manchester Frame example  
Encoder Clock  
Manchester Data  
Binary Data  
1 0 0 1 1 1 1 0 1 0 0 1 0 1 0 1 0  
Start  
Bit  
Data Bits  
(up to 17 data bit)  
Stop  
Bits  
19.3.3.2  
Manchester decoder  
When configured in Manchester mode, the EUSART receiver is able to receive serial frame  
using a 17-bit shift register, an edge detector and several data/control registers. The Manchester  
decoder receives a frame from the RxD pin of the EUSART interface and loads the received  
data in the EUSART data register (UDR and EUDR).  
The bit order of the data bits in the frame is configurable to handle MSB or LSB first.  
The polarity of the bi-phase start is not configurable. The start bit a logical ‘1’ (rising edge at bit  
center).  
The polarity of the stop bits is not configurable, the interface allows to read the 2 stops bits value  
by software.  
The Manchester decoder is enable when the EUSART is configured in Manchester mode and  
the RXEN of USCRB set (global USART receive enable).  
The number of data bits to be received can be configured with the URxS bits of EUCSRA  
register.  
The Manchester decoder provides a special mode where 16 or 17 data bits can be received. In  
this mode the Manchester decoder can automatically detects if the seventeenth bit is Man-  
chester encoded or not (seventeenth data bit or first stop bit). If the receiver detects a valid data  
bit (Manchester transition) during the seventeenth bit time of the frame, the receiver will process  
the frame as a 17-bit frame lenght and set the F1617 bit of EUCSRC register.  
In Manchester mode, the clock used for sampling the EUSART input signal is programmed by  
the baudrate generator.  
The edge detector of the Manchester decoder is based upon a 16 bits up/down counter which  
maximum value can be configured through the MUBRRH and MUBRRL registers.  
213  
4317J–AVR–08/10  
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