The maximum counter value is given by the following formula:
MUBRR[H:L]=FCLKIO / (baud rate frequency)
MBURR[H:L] is used to calibrate the detect window of the start bit and to detect time overflow of
the other bits.
19.3.4
Double Speed Operation (U2X)
Double Speed Operation is controlled by U2X bit in UCSRA. See “Double Speed Operation
(U2X)” on page 186.
This mode of operation is not allowed in manchester bit coding.
Each ‘bit time’ in the Manchester serial frame is divided into two phases (See Figure 19-4). The
counter counts during the first phase and counts down during the second one. When the data bit
transition is detected, the counter memorises the N1 counter value and start counting down.
When the counter reaches the zero value, it starts counting up again and the N1/2 value allows
to open the next detection window. This detection window defines the time zone where the next
data bit edge is sampled.
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AT90PWM2/3/2B/3B
4317J–AVR–08/10
ATMEL [ ATMEL ]
