AT90PWM2/3/2B/3B
Clock Generator
UBRR[H:L]
CLKio
BAUD RATE GENERATOR
SYNC LOGIC
PIN
XCK
CONTROL
Transmitter
TX
CONTROL
EUDR
(Transmit)
UDR
(Transmit)
MANCHESTER
ENCODER
PARITY
GENERATOR
PIN
TxD
TRANSMIT SHIFT REGISTER
CONTROL
Receiver
CLOCK
RX
RECOVERY
CONTROL
MANCHESTER
DECODER
DATA
RECOVERY
PIN
RxD
RECEIVE SHIFT REGISTER
CONTROL
EUDR
UDR
PARITY
(Receive)
(Receive)
CHECKER
UCSRA
UCSRB
UCSRC
EUCSRA
EUCSRB
EUCSRC
•
•
Asynchonous frames
–
–
Standard bit level encoded
Manchester bit encoded
Synchronous frames
In this mode only the Standard bit level encoded is available
–
19.3 Serial Frames
A serial frame is defined to be one character of data bits with synchronization bits (start and stop
bits), and optionally a parity bit for error checking.
19.3.1
Frame Formats
The EUSART allows to receive and transmit serial frame with the following format:
•
1 start bit
•
•
•
•
•
5, 6, 7, 8, 9, 13, 14,15,16,17 data bits
data bits and start bit level encoded or Manchester encoded
data transmition MSB or LSB first (bit ordering)
no, even or odd parity bit
1 or 2 stop bits:
–
–
Stop bits insertion for transmition
Stop bits value read access in reception
211
4317J–AVR–08/10
ATMEL [ ATMEL ]
