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AT90PWM3B-16SU 参数 Datasheet PDF下载

AT90PWM3B-16SU图片预览
型号: AT90PWM3B-16SU
PDF下载: 下载PDF文件 查看货源
内容描述: 8位微控制器具有8K字节的系统内可编程闪存 [8-bit Microcontroller with 8K Bytes In-System Programmable Flash]
分类和应用: 闪存微控制器
文件页数/大小: 361 页 / 6022 K
品牌: ATMEL [ ATMEL ]
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Table 18-12. Examples of UBRR Settings for Commonly Frequencies (Continued)  
fclkio = 12.0000 MHz  
U2X = 0 U2X = 1  
UBRR UBRR  
fclkio = 14.7456 MHz  
U2X = 0 U2X = 1  
UBRR UBRR  
fclkio = 16.0000 MHz  
U2X = 0 U2X = 1  
UBRR UBRR  
Baud  
Rate  
(bps)  
Error  
-0.2%  
0.2%  
0.2%  
0.2%  
0.2%  
0.2%  
-2.5%  
0.2%  
-2.7%  
-8.9%  
11.3%  
0.0%  
Error  
0.0%  
-0.2%  
0.2%  
0.2%  
0.2%  
0.2%  
0.2%  
0.2%  
-2.5%  
0.2%  
-8.9%  
0.0%  
0.0%  
Error  
0.0%  
0.0%  
0.0%  
0.0%  
0.0%  
0.0%  
0.0%  
0.0%  
0.0%  
0.0%  
0.0%  
-7.8%  
-7.8%  
-7.8%  
Error  
0.0%  
0.0%  
0.0%  
0.0%  
0.0%  
0.0%  
0.0%  
0.0%  
0.0%  
0.0%  
0.0%  
5.3%  
-7.8%  
-7.8%  
Error  
-0.1%  
0.2%  
0.2%  
0.6%  
0.2%  
-0.8%  
0.2%  
2.1%  
0.2%  
-3.5%  
8.5%  
0.0%  
0.0%  
0.0%  
Error  
0.0%  
-0.1%  
0.2%  
-0.1%  
0.2%  
0.6%  
0.2%  
-0.8%  
0.2%  
2.1%  
-3.5%  
0.0%  
0.0%  
0.0%  
2400  
4800  
9600  
14.4k  
19.2k  
28.8k  
38.4k  
57.6k  
76.8k  
115.2k  
230.4k  
250k  
312  
155  
77  
51  
38  
25  
19  
12  
9
624  
312  
155  
103  
77  
51  
38  
25  
19  
12  
6
383  
191  
95  
63  
47  
31  
23  
15  
11  
7
767  
383  
191  
127  
95  
63  
47  
31  
23  
15  
7
416  
207  
103  
68  
51  
34  
25  
16  
12  
8
832  
416  
207  
138  
103  
68  
51  
34  
25  
16  
8
6
2
3
3
2
5
3
6
3
7
500k  
2
1
3
1
3
1M  
0
1
0
1
Max. (1)  
750 kbps  
UBRR = 0, Error = 0.0%  
1.5 Mbps  
921.6 kbps  
1.8432 Mbps  
1 Mbps  
2 Mbps  
1.  
19. EUSART (Extended USART)  
The Extended Universal Synchronous and Asynchronous serial Receiver and Transmitter  
(EUSART) provides functionnal extensions to the USART.  
19.1 Features  
19.2 Overview  
Independant bit number configuration for transmit and receive  
Supports Serial Frames with 5, 6, 7, 8, 9 or 13, 14, 15, 16, 17 Data Bits and 1 or 2 Stop Bits  
Biphase Manchester encoder/decoder (for DALI Communications)  
Manchester framing error detection  
Bit ordering (MSB first or LSB first)  
A simplified block diagram of the EUSART Transmitter is shown in Figure 19-1. CPU accessible  
I/O Registers and I/O pins are shown in bold.  
Figure 19-1. EUSART Block Diagram  
The EUSART is activated with the EUSART bit of EUCSRB register. Until this bit is not set, the  
USART will behave as standard USART, all the functionnalities of the EUSART are not  
accessible.  
The EUSART supports more serial frame formats than the standard USART interface:  
210  
AT90PWM2/3/2B/3B  
4317J–AVR–08/10  
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