Figure 16-15. PSCOUTn0 retriggered by PSCn Input A (Edge Retriggering)
On-Time 0
On-Time 1
PSCOUTn0
PSCOUTn1
PSCn Input A
(falling edge)
PSCn Input A
(rising edge)
Dead-Time 0
Dead-Time 1
Note:
This exemple is given in “Input Mode 8” in “2 or 4 ramp mode” See Figure 16-31. for details.
Figure 16-16. PSCOUTn0 retriggered by PSCn Input A (Level Acting)
On-Time 0
On-Time 1
PSCOUTn0
PSCOUTn1
PSCn Input A
(high level)
PSCn Input A
(low level)
Dead-Time 0
Dead-Time 1
Note:
This exemple is given in “Input Mode 1” in “2 or 4 ramp mode” See Figure 16-20. for details.
16.8.3
Retrigger PSCOUTn1 On External Event
PSCOUTn1 ouput can be resetted before end of On-Time 1 on the change on PSCn Input B.
The polarity of PSCn Input B is configurable thanks to a sense control block. PSCn Input B can
be configured to do not act or to act on level or edge modes. PSCn Input B can be the Output of
the analog comparator or the PSCINn input.
As the period of the cycle decreases, the instantaneous frequency of the two outputs increases.
144
AT90PWM2/3/2B/3B
4317J–AVR–08/10
ATMEL [ ATMEL ]
