fractional divider number. The resulting output frequency is the average of the frequencies in the
frame. The fractional divider (d) is given by OCRnRB[15:12].
The PSC output period is directly equal to the PSCOUTn0 On Time + Dead Time (OT0+DT0)
and PSCOUTn1 On Time + DeadTime (OT1+DT1) values. These values are 12 bits numbers.
The frequency adjustment can only be done in steps like the dedicated counters. The step width
is defined as the frequency difference between two neighboring PSC frequencies:
fPLL fPLL
Δf = f1 – f2 = ---------- – ----------- = fPSC
k + 1
1
-------------------
×
k(k + 1)
k
with k is the number of CLKPSC period in a PSC cycle and is given by the following formula:
fPSC
n = ----------
fOP
with fOP is the output operating frequency.
Exemple, in normal mode, with maximum operating frequency 160 kHz and fPLL = 64 Mhz, k
equals 400. The resulting resolution is Delta F equals 64MHz / 400 / 401 = 400 Hz.
In enhanced mode, the output frequency is the average of the frame formed by the 16 consecu-
tive cycles.
16 – d
16
d
16
---------------
------
fAVERAGE
=
× fb1
+
× fb2
fb1 and fb2 are two neightboring base frequencies.
fPLL
fPLL
16 – d
16
d
--------------- ---------- ------ ------------
fAVERAGE
=
×
+
×
n
16 n + 1
Then the frequency resolution is divided by 16. In the example above, the resolution equals 25
Hz.
140
AT90PWM2/3/2B/3B
4317J–AVR–08/10
ATMEL [ ATMEL ]
