AT90USB82/162
• 0 - Reserved
The value read from these bits is always 0. Do not set these bits.
Bit
7
6
5
4
-
3
2
1
0
CFGOK
R
OVERFI
R/W
UNDERFI
R/W
DTSEQ1:0
R
NBUSYBK1:0
R
UESTA0X
Read/Wri
te
R
R
0
R
0
Initial
Value
0
0
0
0
0
0
• 7 - CFGOK - Configuration Status Flag
Set by hardware when the endpoint X size parameter (EPSIZE) and the bank parametrization
(EPBK) are correct compared to the max FIFO capacity and the max number of allowed bank.
This bit is updated when the bit ALLOC is set.
If this bit is cleared, the user should reprogram the UECFG1X register with correct EPSIZE and
EPBK values.
• 6 - OVERFI - Overflow Error Interrupt Flag
Set by hardware when an overflow error occurs in an isochronous endpoint. An interrupt
(EPINTx) is triggered (if enabled).
See Section 20.15, page 206 for more details.
Shall be cleared by software. Setting by software has no effect.
• 5 - UNDERFI - Flow Error Interrupt Flag
Set by hardware when an underflow error occurs in an isochronous endpoint. An interrupt
(EPINTx) is triggered (if enabled).
See Section 20.15, page 206 for more details.
Shall be cleared by software. Setting by software has no effect.
• 4- Reserved
The value read from these bits is always 0. Do not set these bits.
• 3-2 - DTSEQ1:0 - Data Toggle Sequencing Flag
Set by hardware to indicate the PID data of the current bank:
00b Data0
01b Data1
1xb Reserved.
For OUT transfer, this value indicates the last data toggle received on the current bank.
For IN transfer, it indicates the Toggle that will be used for the next packet to be sent. This is not
relative to the current bank.
• 1-0 - NBUSYBK1:0 - Busy Bank Flag
Set by hardware to indicate the number of busy bank.
For IN endpoint, it indicates the number of busy bank(s), filled by the user, ready for IN transfer.
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7707D–AVR–07/08
ATMEL [ ATMEL ]
