AT90USB82/162
Bit
7
6
5
4
3
2
1
0
DAT D7
DAT D6
R/W
DAT D5
R/W
DAT D4
R/W
DAT D3
R/W
DAT D2
R/W
DAT D1
R/W
DAT D0
R/W
UEDATX
Read/Wri R/W
te
Initial
Value
0
0
0
0
0
0
0
0
• 7-0 - DAT7:0 -Data Bits
Set by the software to read/write a byte from/to the endpoint FIFO selected by EPNUM.
Bit
7
6
5
4
3
2
1
0
BYCT D7
R
BYCT D6
R
BYCT D5
R
BYCT D4
R
BYCT D3
R
BYCT D2
R
BYCT D1
R
BYCT D0
R
UEBCLX
R
Read/Wri
te
Initial
Value
0
0
0
0
0
0
0
0
• 7-0 - BYCT7:0 - Byte Count Bits
Set by the hardware. BYCT7:0 is:
- (for IN endpoint) increased after each writing into the endpoint and decremented after each
byte sent,
- (for OUT endpoint) increased after each byte sent by the host, and decremented after each
byte read by the software.
Bit
7
-
6
-
5
-
4
3
2
1
0
EPINT D4
R
EPINT D3
R
EPINT D2
R
EPINT D1
R
EPINT D0
R
UEINT
R
Read/Wri
te
R
R
R
Initial
Value
0
0
0
0
0
0
0
0
• 7-5 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 4-0 - EPINT4:0 - Endpoint Interrupts Bits
Set by hardware when an interrupt is triggered by the UEINTX register and if the corresponding
endpoint interrupt enable bit is set.
Cleared by hardware when the interrupt source is served.
219
7707D–AVR–07/08
ATMEL [ ATMEL ]
