Bit
7
-
6
-
5
-
4
3
-
2
-
1
-
0
-
FNCERR
R/W
UDMFN
Read/Wri
te
R
R
R
R
R
R
R
Initial
Value
0
0
0
0
0
0
0
0
• 7-5 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 4 - FNCERR -Frame Number CRC Error Flag
Set by hardware when a corrupted Frame Number in start of frame packet is received.
This bit and the SOFI interrupt are updated at the same time.
• 3-0 - Reserved
The value read from these bits is always 0. Do not set these bits.
20.18.2 USB device endpoint registers
Bit
7
6
-
5
-
4
-
3
-
2
1
0
-
EPNUM2:0
R/W
UENUM
Read/Wri
te
R
R
R
R
R
R/W
0
R/W
0
Initial
Value
0
0
0
0
0
0
• 7-3 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 2-0 - EPNUM2:0 Endpoint Number Bits
Set to select the number of the endpoint which shall be accessed by the CPU. See Section 20.5,
page 197 for more details.
Values greater than 100b are forbidden.
Bit
7
-
6
-
5
-
4
3
2
1
0
EPRST D4 EPRST D3 EPRST D2 EPRST D1 EPRST D0 UERST
Read/Wri
te
R
R
R
R/W
R/W
R/W
R/W
R/W
Initial
Value
0
0
0
0
0
0
0
0
• 7-5 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 4-0 - EPRST4:0 - Endpoint FIFO Reset Bits
Set to reset the selected endpoint FIFO prior to any other operation, upon hardware reset or
when an USB bus reset has been received. See Section 20.3, page 196 for more information
212
AT90USB82/162
7707D–AVR–07/08
ATMEL [ ATMEL ]
