• 0 - TXINI - Transmitter Ready Interrupt Flag
Set by hardware to signal that the current bank is free and can be filled. An interrupt (EPINTx) is
triggered (if enabled).
Shall be cleared by software to handshake the interrupt. Setting by software has no effect.
This bit is inactive (cleared) if the endpoint is an OUT endpoint.
Bit
7
6
5
-
4
3
2
1
0
FLERRE
NAKINE
R/W
NAKOUTE RXSTPE
RXOUTE
R/W
STALLEDE TXINE
UEIENX
Read/Wri R/W
te
R
R/W
R/W
R/W
R/W
Initial
Value
0
0
0
0
0
0
0
0
• 7 - FLERRE - Flow Error Interrupt Enable Flag
Set to enable an endpoint interrupt (EPINTx) when OVERFI or UNDERFI are sent.
Clear to disable an endpoint interrupt (EPINTx) when OVERFI or UNDERFI are sent.
• 6 - NAKINE - NAK IN Interrupt Enable Bit
Set to enable an endpoint interrupt (EPINTx) when NAKINI is set.
Clear to disable an endpoint interrupt (EPINTx) when NAKINI is set.
• 5 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 4 - NAKOUTE - NAK OUT Interrupt Enable Bit
Set to enable an endpoint interrupt (EPINTx) when NAKOUTI is set.
Clear to disable an endpoint interrupt (EPINTx) when NAKOUTI is set.
• 3 - RXSTPE - Received SETUP Interrupt Enable Flag
Set to enable an endpoint interrupt (EPINTx) when RXSTPI is sent.
Clear to disable an endpoint interrupt (EPINTx) when RXSTPI is sent.
• 2 - RXOUTE - Received OUT Data Interrupt Enable Flag
Set to enable an endpoint interrupt (EPINTx) when RXOUTI is sent.
Clear to disable an endpoint interrupt (EPINTx) when RXOUTI is sent.
• 1 - STALLEDE - Stalled Interrupt Enable Flag
Set to enable an endpoint interrupt (EPINTx) when STALLEDI is sent.
Clear to disable an endpoint interrupt (EPINTx) when STALLEDI is sent.
• 0 - TXINE - Transmitter Ready Interrupt Enable Flag
Set to enable an endpoint interrupt (EPINTx) when TXINI is sent.
Clear to disable an endpoint interrupt (EPINTx) when TXINI is sent.
218
AT90USB82/162
7707D–AVR–07/08
ATMEL [ ATMEL ]
