Table 11. Keypad Interface Signal Description
Signal
Alternate
Function
Name
Type
Description
Keypad Input Lines
Holding one of these pins high or low for 24 oscillator periods triggers a
keypad interrupt.
KIN3:0
I
P1.3:0
Table 12. External Access Signal Description
Signal
Name
Alternate
Function
Type
Description
Address Lines
A15:8
I/O
Upper address lines for the external bus.
Multiplexed higher address and data lines for the IDE interface.
P2.7:0
P0.7:0
Address/Data Lines
Multiplexed lower address and data lines for the external memory or the IDE
interface.
AD7:0
ALE
I/O
O
Address Latch Enable Output
ALE signals the start of an external bus cycle and indicates that valid address
information is available on lines A7:0. An external latch is used to demultiplex
the address from address/data bus.
-
-
ISP Enable Input
This signal must be held to GND through a pull-down resistor at the falling
reset to force execution of the internal bootloader.
ISP
I/O
Read Signal
RD
O
O
P3.7
P3.6
Read signal asserted during external data memory read operation.
Write Signal
Write signal asserted during external data memory write operation.
WR
Table 13. System Signal Description
Signal
Name
Alternate
Function
Type
Description
Reset Input
Holding this pin high for 64 oscillator periods while the oscillator is running
resets the device. The Port pins are driven to their reset conditions when a
voltage lower than VIL is applied, whether or not the oscillator is running.
This pin has an internal pull-down resistor which allows the device to be reset
RST
I
-
by connecting a capacitor between this pin and VDD
.
Asserting RST when the chip is in Idle mode or Power-Down mode returns the
chip to normal operation.
Test Input
TST
I
-
Test mode entry signal. This pin must be set to VDD
.
8
AT89C5132
4173E–USB–09/07
ATMEL [ ATMEL ]
