6. Clock Controller
The AT89C5132 clock controller is based on an on-chip oscillator feeding an on-chip Phase
Lock Loop (PLL). All internal clocks to the peripherals and CPU core are generated by this
controller.
6.1
Oscillator
The AT89C5132 X1 and X2 pins are the input and the output of a single-stage on-chip inverter
(see Figure 6-1) that can be configured with off-chip components such as a Pierce oscillator
(see Figure 6-2). Value of capacitors and crystal characteristics are detailed in the Section “DC
Characteristics”.
The oscillator outputs three different clocks: a clock for the PLL, a clock for the CPU core, and a
clock for the peripherals as shown in Figure 6-1. These clocks are either enabled or disabled,
depending on the power reduction mode as detailed in the section“Power Management” on
page 44. The peripheral clock is used to generate the Timer 0, Timer 1, MMC, ADC, SPI, and
Port sampling clocks.
Figure 6-1. Oscillator Block Diagram and Symbol
0
1
X1
X2
÷ 2
Peripheral
Clock
CPU Core
Clock
X2
CKCON.0
IDL
PCON.0
PD
PCON.1
Oscillator
Clock
PER
CLOCK
CPU
CLOCK
OSC
CLOCK
Peripheral Clock Symbol
CPU Core Clock Symbol
Oscillator Clock Symbol
Figure 6-2. Crystal Connection
X1
C1
Q
C2
VSS
X2
6.2
X2 Feature
Unlike standard C51 products that require 12 oscillator clock periods per machine cycle, the
AT89C5132 needs only 6 oscillator clock periods per machine cycle. This feature called the “X2
feature” can be enabled using the X2 bit(1) in CKCON (see Table 1) and allows the AT89C5132
to operate in 6 or 12 oscillator clock periods per machine cycle. As shown in Figure 6-1, both
CPU and peripheral clocks are affected by this feature. Figure 6-3 shows the X2 mode switching
waveforms. After reset, the standard mode is activated. In standard mode, the CPU and periph-
12
AT89C5132
4173E–USB–09/07
ATMEL [ ATMEL ]
