When the AT85C51SND3Bx is the only slave on the bus, it can be useful not to use SS
pin and get it back to I/O functionality. This is achieved by setting SSDIS bit in SPCON.
This bit has no effect when CPHA is cleared (see Section "SS Management",
page 227).
Figure 118. SPI Slave Mode Block Diagram
MISO/P3.0
SPSCR.2
SPDAT WR
UARTM
MOSI/P3.1
I
Q
8-bit Shift Register
SPDAT RD
SCK/P3.2
SS/P3.3
MODF
SPSCR.4
OVR
Control
and
Clock Logic
SPSCR.6
SPIF
SPSCR.7
SSDIS
SPCON.5
SPTE
SPSCR.3
CPHA
SPCON.2
CPOL
SPCON.3
Note:
MSTR bit in SPCON is cleared to select slave mode.
Bit Rate
In master mode, the bit rate can be selected from seven predefined bit rates using the
SPR2, SPR1 and SPR0 control bits in SPCON according to Table 250. These bit rates
are derived from the peripheral clock (FPER) issued from the Clock Controller block as
detailed in Section "Clock Controller", page 27.
In slave mode, the maximum baud rate allowed on the SCK input is limited to FOSC ÷ 4.
Table 250. Serial Bit Rates
Bit Rate (kHz) Vs FPER (MHz)
SPR2 SPR1 SPR0
6(1)
3000
1500
750
8(1)
4000
2000
1000
500
250
125
62.5
-
10(1)
5000
2500
1250
625
12(1)(2)
6000
3000
1500
750
16(2)
8000
4000
2000
1000
500
250
125
-
20(2)
10000
5000
2500
1250
625
24(2)
12000
6000
3000
1500
750
FPER Divider
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2
4
8
16
375
187.5
93.75
46.875
-
312.5
156.25
78.125
-
375
32
187.5
93.75
-
312.5
156.25
-
375
64
187.5
-
128
Reserved
Notes: 1. These frequencies are achieved in X1 mode, FPER = FOSC ÷ 2.
2. These frequencies are achieved in X2 mode, FPER = FOSC
.
226
AT85C51SND3Bx
7632A–MP3–03/06
ATMEL [ ATMEL ]
