Table 112. Dac Miscellaneous Register - DAC_ MISC (0Ah)
7
6
5
4
3
2
1
0
-
-
DINTSEL1 DINTSEL0
DITHEN
DEEMPEN
NBITS1
NBITS0
Bit
Bit
Mnemonic Description
Number
7
-
-
Not used
6
5:4
3
Not used
DINTSEL1:0 I2S data format selector
DITHEN
Dither enable (Clear this bit to disable, set to enable)
2
DEEMPEN
NBITS 1:0
De-emphasis enable (clear this bit to disable, set to enable)
Data interface word length
1:0
Reset Value = 00000010b
Table 113. DAC Precharge Control Register - DAC_ PRECH (0Ch)
7
6
5
4
3
2
1
0
-
-
PRCHAR
GEPADRV
PRCHAR
GELNOL
PRCHAR
GELNIL
PRCHAR
GELNIL
PRCHAR
GE
PRCHAR
GEAUXIN
PRCHAR
GELNOR
ONMSTR
Bit
Bit
Mnemonic
Description
Number
Differential mono PA driver pre-charge.
Set to charge.
PRCHARGEPAD
RV
7
6
5
4
3
2
1
0
Differential mono auxiliary input pre-charge.
Set to charge.
PRCHARGEAUX
IN
Right channel line out pre-charge.
Set to charge.
PRCHARGELNO
R
Left channel line out pre-charge.
Set to charge.
PRCHARGELNO
L
Right channel line in pre-charge.
Set to charge.
PRCHARGELNI
R
Left channel line in pre-charge
Set to charge.
PRCHARGELNIL
PRCHARGE
ONMSTR
Master pre-charge
Set to charge.
Master power on control
Clear to power down. Set to to power up.
Reset Value = 00000000b
96
AT8xC51SND2C
4341D–MP3–04/05
ATMEL [ ATMEL ]
