Example Start I2S
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Start DCLK.
RSTMASK=1.
RESFILZ=0 and RSTZ=0.
RESFILZ=1 and RSTZ=1.
RSTMASK=0.
Delay 5 ms.
ONDACL=1 and ONDACR=1.
Program all DAC settings: audio format, gains...
Example Stop I2S:
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DAC off: ONDACL=0 and ONDACR=0.
Stop I2S and DLCK.
Audio PA Sequence
PA Power-On Sequence
To avoid an audible ‘click’ at start-up, the input capacitors have to be pre-charged
before the Power Amplifier.
PA Power-Off Sequence
To avoid an audible ‘click’ at power-off, the gain should be set to the minimum gain (-
22dB) before setting the Power Amplifier.
Precharge Control
The power up of the circuit can be performed independently for several blocks. The
sequence flow starts by setting to High the block specific fastcharge control bit and sub-
sequently the associated power control bit. Once the power control bit is set to High, the
fast charging starts. This action begins a user controlled fastcharge cycle. When the
fastcharge period is over, the user must reset the associated fastcharge bit and the
block is ready for use. If a power control bit is cleared a new power up sequence is
needed.
The several blocks with independent power control are identified in Table 118. The table
describes the power on control and fastcharge bits for each block.
Table 118. Precharge and Power Control
Powered up block
Power on control bit
Precharge Control Bit
PRCHARGE
(reg 12; bit 1)
Vref & Vcm generator
ONMSTR
Left line in amplifier
Right line in amplifier
Left line out amplifier
Right line out amplifier
Left D-to-A converter
Right D-to-A converter
Auxiliary input amplifier
PA Driver output
ONLNIL
ONLNIR
PRCHARGELNIL
PRCHARGELNIR
PRCHARGELNOL
PRCHARGELNOR
Not needed
ONLNOL
ONLNOR
ONDACL
ONDACR
ONAUXIN
ONPADRV
Not needed
PRCHARGEAUXIN
PRCHARGEPADRV
Note:
Note that all block can be precharged simultaneously.
100
AT8xC51SND2C
4341D–MP3–04/05