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83C51SND2C-JL 参数 Datasheet PDF下载

83C51SND2C-JL图片预览
型号: 83C51SND2C-JL
PDF下载: 下载PDF文件 查看货源
内容描述: 单芯片闪存微控制器与MP3解码器,支持完整的音频接口 [Single-Chip Flash Microcontroller with MP3 Decoder with Full Audio Interface]
分类和应用: 解码器闪存微控制器
文件页数/大小: 235 页 / 2877 K
品牌: ATMEL [ ATMEL ]
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AT8xC51SND2C  
Serial I/O Port  
The serial I/O port in the AT8xC51SND2C provides both synchronous and asynchro-  
nous communication modes. It operates as a Synchronous Receiver and Transmitter in  
one single mode (Mode 0) and operates as an Universal Asynchronous Receiver and  
Transmitter (UART) in three full-duplex modes (Modes 1, 2 and 3). Asynchronous  
modes support framing error detection and multiprocessor communication with auto-  
matic address recognition.  
Mode Selection  
SM0 and SM1 bits in SCON register (see Figure 160) are used to select a mode among  
the single synchronous and the three asynchronous modes according to Table 158.  
Table 158. Serial I/O Port Mode Selection  
SM0  
SM1  
Mode  
Description  
Baud Rate  
Fixed/Variable  
Variable  
0
0
1
1
0
1
0
1
0
1
2
3
Synchronous Shift Register  
8-bit UART  
9-bit UART  
Fixed  
9-bit UART  
Variable  
Baud Rate Generator  
Depending on the mode and the source selection, the baud rate can be generated from  
either the Timer 1 or the Internal Baud Rate Generator. The Timer 1 can be used in  
Modes 1 and 3 while the Internal Baud Rate Generator can be used in Modes 0, 1  
and 3.  
The addition of the Internal Baud Rate Generator allows freeing of the Timer 1 for other  
purposes in the application. It is highly recommended to use the Internal Baud Rate  
Generator as it allows higher and more accurate baud rates than Timer 1.  
Baud rate formulas depend on the modes selected and are given in the following mode  
sections.  
Timer 1  
When using Timer 1, the Baud Rate is derived from the overflow of the timer. As shown  
in Figure 114 Timer 1 is used in its 8-bit auto-reload mode (detailed in Section "Mode 2  
(8-bit Timer with Auto-Reload)", page 53). SMOD1 bit in PCON register allows doubling  
of the generated baud rate.  
Figure 114. Timer 1 Baud Rate Generator Block Diagram  
PER  
CLOCK  
÷ 6  
0
1
Overflow  
TL1  
(8 bits)  
÷ 2  
0
1
To serial  
Port  
T1  
C/T1#  
TMOD.6  
SMOD1  
PCON.7  
INT1  
TH1  
(8 bits)  
GATE1  
TMOD.7  
T1  
CLOCK  
TR1  
TCON.6  
169  
4341D–MP3–04/05  
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