Table 156. SPSTA Register
SPSTA (S:C4h) – SPI Status Register
7
6
5
-
4
3
-
2
-
1
-
0
-
SPIF
WCOL
MODF
Bit
Bit
Number
Mnemonic Description
SPI Interrupt Flag
Set by hardware when an 8-bit shift is completed.
7
SPIF
Cleared by hardware when reading or writing SPDAT after reading SPSTA.
Write Collision Flag
6
5
WCOL
Set by hardware to indicate that a collision has been detected.
Cleared by hardware to indicate that no collision has been detected.
Reserved
-
The value read from this bit is indeterminate. Do not set this bit.
Mode Fault
4
MODF
-
Set by hardware to indicate that the SS pin is at an appropriate level.
Cleared by hardware to indicate that the SS pin is at an inappropriate level.
Reserved
3 - 0
The value read from these bits is indeterminate. Do not set these bits.
Reset Value = 00000 0000b
Table 157. SPDAT Register
SPDAT (S:C5h) – Synchronous Serial Data Register
7
6
5
4
3
2
1
0
SPD7
SPD6
SPD5
SPD4
SPD3
SPD2
SPD1
SPD0
Bit
Bit
Number
Mnemonic Description
7 - 0
SPD7:0 Synchronous Serial Data.
Reset Value = XXXX XXXXb
168
AT8xC51SND2C
4341D–MP3–04/05
ATMEL [ ATMEL ]
