欢迎访问ic37.com |
会员登录 免费注册
发布采购

83C51SND2C-JL 参数 Datasheet PDF下载

83C51SND2C-JL图片预览
型号: 83C51SND2C-JL
PDF下载: 下载PDF文件 查看货源
内容描述: 单芯片闪存微控制器与MP3解码器,支持完整的音频接口 [Single-Chip Flash Microcontroller with MP3 Decoder with Full Audio Interface]
分类和应用: 解码器闪存微控制器
文件页数/大小: 235 页 / 2877 K
品牌: ATMEL [ ATMEL ]
 浏览型号83C51SND2C-JL的Datasheet PDF文件第168页浏览型号83C51SND2C-JL的Datasheet PDF文件第169页浏览型号83C51SND2C-JL的Datasheet PDF文件第170页浏览型号83C51SND2C-JL的Datasheet PDF文件第171页浏览型号83C51SND2C-JL的Datasheet PDF文件第173页浏览型号83C51SND2C-JL的Datasheet PDF文件第174页浏览型号83C51SND2C-JL的Datasheet PDF文件第175页浏览型号83C51SND2C-JL的Datasheet PDF文件第176页  
Asynchronous Modes  
(Modes 1, 2 and 3)  
The Serial Port has one 8-bit and 2 9-bit asynchronous modes of operation. Figure 121  
shows the Serial Port block diagram in such asynchronous modes.  
Figure 121. Serial I/O Port Block Diagram (Modes 1, 2 and 3)  
SCON.6  
SCON.7  
SCON.3  
SM1  
SM0  
TB8  
SBUF Tx SR  
Rx SR  
TXD  
RXD  
Mode Decoder  
M3 M2 M1 M0  
T1  
CLOCK  
IBRG  
CLOCK  
Mode & Clock  
Controller  
SBUF Rx  
RB8  
SCON.2  
PER  
CLOCK  
SM2  
SCON.4  
TI  
SCON.1  
RI  
SCON.0  
Mode 1  
Mode 1 is a full-duplex, asynchronous mode. The data frame (see Figure 122) consists  
of 10 bits: one start, eight data bits and one stop bit. Serial data is transmitted on the  
TXD pin and received on the RXD pin. When a data is received, the stop bit is read in  
the RB8 bit in SCON register.  
Figure 122. Data Frame Format (Mode 1)  
Mode 1  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
Start bit  
8-bit data  
Stop bit  
Modes 2 and 3  
Modes 2 and 3 are full-duplex, asynchronous modes. The data frame (see Figure 123)  
consists of 11 bits: one start bit, eight data bits (transmitted and received LSB first), one  
programmable ninth data bit and one stop bit. Serial data is transmitted on the TXD pin  
and received on the RXD pin. On receive, the ninth bit is read from RB8 bit in SCON  
register. On transmit, the ninth data bit is written to TB8 bit in SCON register. Alterna-  
tively, you can use the ninth bit can be used as a command/data flag.  
Figure 123. Data Frame Format (Modes 2 and 3)  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
D8  
Start bit  
9-bit data  
Stop bit  
Transmission (Modes 1, 2  
and 3)  
To initiate a transmission, write to SCON register, set the SM0 and SM1 bits according  
to Table 158, and set the ninth bit by writing to TB8 bit. Then, writing the Byte to be  
transmitted to SBUF register starts the transmission.  
Reception (Modes 1, 2 and 3)  
To prepare for reception, write to SCON register, set the SM0 and SM1 bits according to  
Table 158, and set the REN bit. The actual reception is then initiated by a detected high-  
to-low transition on the RXD pin.  
172  
AT8xC51SND2C  
4341D–MP3–04/05  
 复制成功!