AT8xC51SND2C
Framing Error Detection
(Modes 1, 2 and 3)
Framing error detection is provided for the three asynchronous modes. To enable the
framing bit error detection feature, set SMOD0 bit in PCON register as shown in
Figure 124.
When this feature is enabled, the receiver checks each incoming data frame for a valid
stop bit. An invalid stop bit may result from noise on the serial lines or from simultaneous
transmission by 2 devices. If a valid stop bit is not found, the software sets FE bit in
SCON register.
Software may examine FE bit after each reception to check for data errors. Once set,
only software or a chip reset clear FE bit. Subsequently received frames with valid stop
bits cannot clear FE bit. When the framing error detection feature is enabled, RI rises on
stop bit instead of the last data bit as detailed in Figure 130.
Figure 124. Framing Error Block Diagram
Framing Error
Controller
FE
1
0
SM0/FE
SCON.7
SM0
SMOD0
PCON.6
Baud Rate Selection (Modes 1 In modes 1 and 3, the Baud Rate is derived either from the Timer 1 or the Internal Baud
and 3)
Rate Generator and allows different baud rate in reception and transmission.
As shown in Figure 125 the selection is done using RBCK and TBCK bits in BDRCON
register.
Figure 126 gives the baud rate calculation formulas for each baud rate source while
Table 159 details Internal Baud Rate Generator configuration for different peripheral
clock frequencies and giving baud rates closer to the standard baud rates.
Figure 125. Baud Rate Source Selection (Modes 1 and 3)
T1
T1
CLOCK
CLOCK
0
0
1
To Serial
Rx Port
To Serial
Tx Port
÷ 16
÷ 16
1
IBRG
CLOCK
IBRG
CLOCK
RBCK
BDRCON.2
TBCK
BDRCON.3
Figure 126. Baud Rate Formulas (Modes 1 and 3)
2SMOD1 ⋅ FPER
2SMOD1 ⋅ FPER
6 ⋅ 32 ⋅ (256 -TH1)
Baud_Rate=
Baud_Rate=
TH1= 256 -
6(1-SPD) ⋅ 32 ⋅ (256 -BRL)
2SMOD1 ⋅ FPER
6(1-SPD) ⋅ 32 ⋅ Baud_Rate
2SMOD1 ⋅ FPER
192 ⋅ Baud_Rate
BRL= 256 -
a. IBRG Formula
b. T1 Formula
173
4341D–MP3–04/05
ATMEL [ ATMEL ]
