Master Mode with Interrupt
Figure 111 shows the initialization phase and the transfer phase flows using the inter-
rupt. Using this flow prevents any overrun error occurrence.
The bit rate is selected according to Table 154.
The transfer format depends on the slave peripheral.
SS may be deasserted between transfers depending also on the slave peripheral.
Reading SPSTA at the beginning of the ISR is mandatory for clearing the SPIF flag.
Clear is effective when reading SPDAT.
Figure 111. Master SPI Interrupt Flows
SPI Initialization
Interrupt Policy
SPI Interrupt
Service Routine
Select Master Mode
Read Status
MSTR = 1
Read SPSTA
Select Bit Rate
Get Data Received
program SPR2:0
read SPDAT
Select Format
Start New Transfer
program CPOL & CPHA
write data in SPDAT
Enable interrupt
ESPI =1
Last Transfer?
Enable SPI
SPEN = 1
Deselect Slave
Pn.x = H
Select Slave
Pn.x = L
Disable interrupt
SPIE = 0
Start Transfer
write data in SPDAT
164
AT8xC51SND2C
4341D–MP3–04/05
ATMEL [ ATMEL ]
