AT8xC51SND2C
Registers
Table 145. MMCON0 Register
MMCON0 (S:E4h) – MMC Control Register 0
7
6
5
4
3
2
1
0
DRPTR
DTPTR
CRPTR
CTPTR
MBLOCK
DFMT
RFMT
CRCDIS
Bit
Bit
Number
Mnemonic Description
Data Receive Pointer Reset Bit
7
6
5
4
3
2
1
0
DRPTR Set to reset the read pointer of the data FIFO.
Clear to release the read pointer of the data FIFO.
Data Transmit Pointer Reset Bit
DTPTR
Set to reset the write pointer of the data FIFO.
Clear to release the write pointer of the data FIFO.
Command Receive Pointer Reset Bit
CRPTR Set to reset the read pointer of the receive command FIFO.
Clear to release the read pointer of the receive command FIFO.
Command Transmit Pointer Reset Bit
CTPTR
Set to reset the write pointer of the transmit command FIFO.
Clear to release the read pointer of the transmit command FIFO.
Multi-block Enable Bit
MBLOCK Set to select multi-block data format.
Clear to select single block data format.
Data Format Bit
DFMT
RFMT
Set to select the block-oriented data format.
Clear to select the stream data format.
Response Format Bit
Set to select the 48-bit response format.
Clear to select the 136-bit response format.
CRC7 Disable Bit
CRCDIS Set to disable the CRC7 computation when receiving a response.
Clear to enable the CRC7 computation when receiving a response.
Reset Value = 0000 0000b
151
4341D–MP3–04/05
ATMEL [ ATMEL ]
