AT8xC51SND2C
Figure 100. Data Block Reception Flows
Data Block
Reception
Data Block
Initialization
Data Block
Reception ISR
Start Transmission
DATEN = 1
Unmask FIFOs Full
F1FM = 0
FIFO Full?
F1EI or F2EI = 1?
DATEN = 0
F2FM = 0
Start Transmission
DATEN = 1
FIFO Reading
read 8 data from MMDAT
FIFO Full?
F1EI or F2EI = 1?
DATEN = 0
No More Data
To Receive?
FIFO Reading
read 8 data from MMDAT
Mask FIFOs Full
F1FM = 1
No More Data
To Receive?
F2FM = 1
a. Polling mode
b. Interrupt mode
Flow Control
To allow transfer at high speed without taking care of CPU oscillator frequency, the
FLOWC bit in MMCON2 allows control of the data flow in both transmission and
reception.
During transmission, setting the FLOWC bit has the following effects:
•
•
MMCLK is stopped when both FIFOs become empty: F1EI and F2EI set.
MMCLK is restarted when one of the FIFOs becomes full: F1EI or F2EI cleared.
During reception, setting the FLOWC bit has the following effects:
•
•
MMCLK is stopped when both FIFOs become full: F1FI and F2FI set.
MMCLK is restarted when one of the FIFOs becomes empty: F1FI or F2FI cleared.
As soon as the clock is stopped, the MMC bus is frozen and remains in its state until the
clock is restored by writing or reading data in MMDAT.
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4341D–MP3–04/05
ATMEL [ ATMEL ]
