AT8xC51SND2C
Table 130. UEPINT Register
UEPINT (S:F8h Read-only) – USB Endpoint Interrupt Register
7
-
6
-
5
-
4
-
3
-
2
1
0
EP2INT
EP1INT
EP0INT
Bit
Bit
Number
Mnemonic Description
Reserved
7 - 3
-
The value read from these bits is always 0. Do not set these bits.
Endpoint 2 Interrupt Flag
This bit is set by hardware when an endpoint interrupt source has been detected
on the endpoint 2. The endpoint interrupt sources are in the UEPSTAX register
and can be: TXCMP, RXOUTB0, RXOUTB1, RXSETUP or STLCRC.
2
EP2INT
EP1INT
EP0INT
A USB interrupt is triggered when the EP2IE bit in the UEPIEN register is set.
This bit is cleared by hardware when all the endpoint interrupt sources are
cleared.
Endpoint 1 Interrupt Flag
This bit is set by hardware when an endpoint interrupt source has been detected
on the endpoint 1. The endpoint interrupt sources are in the UEPSTAX register
and can be: TXCMP, RXOUTB0, RXOUTB1, RXSETUP or STLCRC.
1
A USB interrupt is triggered when the EP1IE bit in the UEPIEN register is set.
This bit is cleared by hardware when all the endpoint interrupt sources are
cleared.
Endpoint 0 Interrupt Flag
This bit is set by hardware when an endpoint interrupt source has been detected
on the endpoint 0. The endpoint interrupt sources are in the UEPSTAX register
and can be: TXCMP, RXOUTB0, RXOUTB1, RXSETUP or STLCRC.
0
A USB interrupt is triggered when the EP0IE bit in the UEPIEN register is set.
This bit is cleared by hardware when all the endpoint interrupt sources are
cleared.
Reset Value = 0000 0000b
Table 131. UEPDATX Register
UEPDATX (S:CFh) – USB Endpoint X FIFO Data Register (X = EPNUM set in UEPNUM)
7
6
5
4
3
2
1
0
FDAT7
FDAT6
FDAT5
FDAT4
FDAT3
FDAT2
FDAT1
FDAT0
Bit
Bit
Number
Mnemonic Description
Endpoint X FIFO Data
7 - 0
FDAT7:0 Data Byte to be written to FIFO or data Byte to be read from the FIFO, for the
Endpoint X (see EPNUM).
Reset Value = XXh
129
4341D–MP3–04/05
ATMEL [ ATMEL ]
