AT8xC51SND2C
Table 134. UFNUMH Register
UFNUMH (S:BBh, Read-only) – USB Frame Number High Register
7
-
6
-
5
4
3
-
2
1
0
CRCOK
CRCERR
FNUM10
FNUM9
FNUM8
Bit
Bit
Number
Mnemonic Description
Reserved
7 - 3
-
The value read from these bits is always 0. Do not set these bits.
Frame Number CRC OK Bit
Set by hardware after a non corrupted Frame Number in Start of Frame Packet is
received.
5
CRCOK
Updated after every Start Of Frame packet reception.
Note: The Start Of Frame interrupt is generated just after the PID receipt.
Frame Number CRC Error Bit
Set by hardware after a corrupted Frame Number in Start of Frame Packet is
received.
4
CRCERR
Updated after every Start Of Frame packet reception.
Note: The Start Of Frame interrupt is generated just after the PID receipt.
Reserved
3
-
The value read from this bits is always 0. Do not set this bit.
Frame Number
2-0
FNUM10:8 Upper 3 bits of the 11-bit Frame Number. It is provided in the last received SOF
packet. FNUM does not change if a corrupted SOF is received.
Reset Value = 00h
Table 135. USBCLK Register
USBCLK (S:EAh) – USB Clock Divider Register
7
-
6
-
5
-
4
-
3
-
2
-
1
0
USBCD1
USBCD0
Bit
Bit
Number
Mnemonic Description
Reserved
7 - 2
1 - 0
-
The value read from these bits is always 0. Do not set these bits.
USB Controller Clock Divider
2-bit divider for USB controller clock generation.
USBCD1:0
Reset Value = 0000 0000b
131
4341D–MP3–04/05
ATMEL [ ATMEL ]
