Table 128. UEPRST Register
UEPRST (S:D5h) – USB Endpoint FIFO Reset Register
7
-
6
-
5
-
4
-
3
-
2
1
0
EP2RST
EP1RST
EP0RST
Bit
Bit
Number
Mnemonic Description
Reserved
7 - 3
2
-
The value read from these bits is always 0. Do not set these bits.
Endpoint 2 FIFO Reset
EP2RST Set and clear to reset the endpoint 2 FIFO prior to any other operation, upon
hardware reset or when an USB bus reset has been received.
Endpoint 1 FIFO Reset
1
0
EP1RST Set and clear to reset the endpoint 1 FIFO prior to any other operation, upon
hardware reset or when an USB bus reset has been received.
Endpoint 0 FIFO Reset
EP0RST Set and clear to reset the endpoint 0 FIFO prior to any other operation, upon
hardware reset or when an USB bus reset has been received.
Reset Value = 0000 0000b
Table 129. UEPIEN Register
UEPIEN (S:C2h) – USB Endpoint Interrupt Enable Register
7
-
6
-
5
-
4
-
3
-
2
1
0
EP2INTE
EP1INTE
EP0INTE
Bit
Bit
Number
Mnemonic Description
Reserved
7 - 3
2
-
The value read from these bits is always 0. Do not set these bits.
Endpoint 2 Interrupt Enable Bit
EP2INTE Set to enable the interrupts for endpoint 2.
Clear this bit to disable the interrupts for endpoint 2.
Endpoint 1 Interrupt Enable Bit
1
0
EP1INTE Set to enable the interrupts for the endpoint 1.
Clear to disable the interrupts for the endpoint 1.
Endpoint 0 Interrupt Enable Bit
EP0INTE Set to enable the interrupts for the endpoint 0.
Clear to disable the interrupts for the endpoint 0.
Reset Value = 0000 0000b
128
AT8xC51SND2C
4341D–MP3–04/05
ATMEL [ ATMEL ]
