AT8xC51SND2C
Table 126. UEPCONX Register
UEPCONX (S:D4h) – USB Endpoint X Control Register (X = EPNUM set in UEPNUM)
7
6
5
4
3
2
1
0
EPEN
NAKIEN
NAKOUT
NAKIN
DTGL
EPDIR
EPTYPE1
EPTYPE0
Bit
Bit
Number
Mnemonic Description
Endpoint Enable Bit
Set to enable the endpoint according to the device configuration. Endpoint 0
should always be enabled after a hardware or USB bus reset and participate in
the device configuration.
7
6
5
EPEN
Clear to disable the endpoint according to the device configuration.
NAK Interrupt enable
Set this bit to enable NAK IN or NAK OUT interrupt.
Clear this bit to disable NAK IN or NAK OUT Interrupt.
NAKIEN
NAK OUT received
This bit is set by hardware when an NAK handshake has been sent in response
NAKOUT of a OUT request from the Host. This triggers a USB interrupt when NAKIEN is
set.
This bit should be cleared by software.
NAK IN received
This bit is set by hardware when an NAK handshake has been sent in response
of a IN request from the Host. This triggers a USB interrupt when NAKIEN is set.
This bit should be cleared by software.
4
3
2
NAKIN
Data Toggle Status Bit (Read-only)
Set by hardware when a DATA1 packet is received.
Cleared by hardware when a DATA0 packet is received.
DTGL
Endpoint Direction Bit
Set to configure IN direction for Bulk, Interrupt and Isochronous endpoints.
Clear to configure OUT direction for Bulk, Interrupt and Isochronous endpoints.
This bit has no effect for Control endpoints.
EPDIR
Endpoint Type Bits
Set this field according to the endpoint configuration (Endpoint 0 should always
be configured as Control):
1-0
EPTYPE1:0 00 Control endpoint
01 Isochronous endpoint
10 Bulk endpoint
11 Interrupt endpoint
Reset Value = 1000 0000b
125
4341D–MP3–04/05
ATMEL [ ATMEL ]
