Table 127. UEPSTAX Register
UEPSTAX (S:CEh) – USB Endpoint X Status and Control Register (X = EPNUM set in UEPNUM)
7
6
5
4
3
2
1
0
DIR
RXOUTB1 STALLRQ
TXRDY
STLCRC
RXSETUP RXOUTB0
TXCMP
Bit
Bit
Number
Mnemonic Description
Control Endpoint Direction Bit
This bit is relevant only if the endpoint is configured in Control type.
Set for the data stage. Clear otherwise.
7
DIR
Note: This bit should be configured on RXSETUP interrupt before any other bit is
changed. This also determines the status phase (IN for a control write and OUT
for a control read). This bit should be cleared for status stage of a Control Out
transaction.
Received OUT Data Bank 1 for Endpoints 1 and 2 (Ping-pong mode)
This bit is set by hardware after a new packet has been stored in the endpoint
FIFO data bank 1 (only in Ping-pong mode). Then, the endpoint interrupt is
triggered if enabled and all the following OUT packets to the endpoint bank 1 are
rejected (NAK’ed) until this bit has been cleared, excepted for Isochronous
Endpoints.
6
RXOUTB1
This bit should be cleared by the device firmware after reading the OUT data
from the endpoint FIFO.
126
AT8xC51SND2C
4341D–MP3–04/05
ATMEL [ ATMEL ]
