Table 124. USBIEN Register
USBIEN (S:BEh) – USB Global Interrupt Enable Register
7
-
6
-
5
4
3
2
-
1
-
0
EWUPCPU EEORINT
ESOFINT
ESPINT
Bit
Bit
Number
Mnemonic Description
Reserved
7 - 6
5
-
The value read from these bits is always 0. Do not set these bits.
Wake Up CPU Interrupt Enable Bit
EWUPCPU Set to enable the Wake Up CPU interrupt.
Clear to disable the Wake Up CPU interrupt.
End Of Reset Interrupt Enable Bit
4
EEOFINT Set to enable the End Of Reset interrupt. This bit is set after reset.
Clear to disable End Of Reset interrupt.
Start Of Frame Interrupt Enable Bit
ESOFINT Set to enable the SOF interrupt.
Clear to disable the SOF interrupt.
3
2 - 1
0
Reserved
-
The value read from these bits is always 0. Do not set these bits.
Suspend Interrupt Enable Bit
ESPINT
Set to enable Suspend interrupt.
Clear to disable Suspend interrupt.
Reset Value = 0001 0000b
Table 125. UEPNUM Register
UEPNUM (S:C7h) – USB Endpoint Number
7
-
6
-
5
-
4
-
3
-
2
-
1
0
EPNUM1
EPNUM0
Bit
Bit
Number
Mnemonic Description
Reserved
7 - 2
1 - 0
-
The value read from these bits is always 0. Do not set these bits.
Endpoint Number Bits
EPNUM1:0 Set this field with the number of the endpoint which should be accessed when
reading or writing to registers UEPSTAX, UEPDATX, UBYCTX or UEPCONX.
Reset Value = 0000 0000b
124
AT8xC51SND2C
4341D–MP3–04/05
ATMEL [ ATMEL ]
