USB Interrupt System
Interrupt System Priorities
Figure 76. USB Interrupt Control System
00
01
10
11
D+
USB
Controller
D-
EUSB
IE1.6
EA
IE0.7
IPH/L
Interrupt Enable
Priority Enable
Lowest Priority Interrupts
Table 1. Priority Levels
IPHUSB
IPLUSB
USB Priority Level
0
0
1
1
0
1
0
1
0..................Lowest
1
2
3..................Highest
USB Interrupt Control System As shown in Figure 77, many events can produce a USB interrupt:
•
•
•
TXCMPL: Transmitted In Data (Table 127 on page 126). This bit is set by hardware
when the Host accept a In packet.
RXOUTB0: Received Out Data Bank 0 (Table 127 on page 126). This bit is set by
hardware when an Out packet is accepted by the endpoint and stored in bank 0.
RXOUTB1: Received Out Data Bank 1 (only for Ping-pong endpoints) (Table 127 on
page 126). This bit is set by hardware when an Out packet is accepted by the
endpoint and stored in bank 1.
•
•
RXSETUP: Received Setup (Table 127 on page 126). This bit is set by hardware
when an SETUP packet is accepted by the endpoint.
STLCRC: STALLED (only for Control, Bulk and Interrupt endpoints) (Table 127 on
page 126). This bit is set by hardware when a STALL handshake has been sent as
requested by STALLRQ, and is reset by hardware when a SETUP packet is
received.
•
•
•
SOFINT: Start of Frame Interrupt (Table 123 on page 123). This bit is set by
hardware when a USB start of frame packet has been received.
WUPCPU: Wake-Up CPU Interrupt (Table 123 on page 123). This bit is set by
hardware when a USB resume is detected on the USB bus, after a SUSPEND state.
SPINT: Suspend Interrupt (Table 123 on page 123). This bit is set by hardware
when a USB suspend is detected on the USB bus.
120
AT8xC51SND2C
4341D–MP3–04/05
ATMEL [ ATMEL ]
