AS3525-A/-B C22O22
Data Sheet, Confidential
GPIO raw interrupt status register
Table 35 GPIO raw interrupt status register
Name
Base
Default
GPIO1_RIS
GPIO2_RIS
GPIO3_RIS
GPIO4_RIS
AS3525_GPIO1_BASE
AS3525_GPIO2_BASE
AS3525_GPIO3_BASE
AS3525_GPIO4_BASE
0xC80B0000
0xC80C0000
0xC80D0000
0xC80E0000
GPIO raw interrupt status register
Bits read HIGH reflect the status of interrupts trigger conditions detected (raw, prior to
masking), indicating that all the requirements have been met, before they are finally
allowed to trigger by GPIO interrupt mask register (GPIO1_IE, ...). Bits read as LOW
indicate that corresponding input pins have not initiated an interrupt. This register is
read only, its bits are cleared by a reset.
Offset: 0x414
Bit
Bit Name
Default
Access
Bit Description
7:0
GPIO raw interrupt
status register
00000000
R
Reflect the status of interrupts trigger conditions detection on
pins (raw, prior to masking).
0: requirements not met on corresponding pins.
1: requirements met by corresponding pins.
GPIO masked interrupt status register
Table 36 GPIO masked interrupt status register
Name
Base
Default
GPIO1_MIS
GPIO2_MIS
GPIO3_MIS
GPIO4_MIS
AS3525_GPIO1_BASE
AS3525_GPIO2_BASE
AS3525_GPIO3_BASE
AS3525_GPIO4_BASE
0xC80B0000
0xC80C0000
0xC80D0000
0xC80E0000
GPIO masked interrupt status register
Bits read HIGH reflect the status of input lines triggering an interrupt. Bits read as LOW
indicate that either no interrupt has been generated, or the interrupt is masked. This
register shows the state of the interrupt after masking. This register is read-only. All
bits are cleared by a reset. The contents of this register are made available externally
through the intra-chip (or on-chip) GPIO1_MIS, ... signals.
Offset: 0x418
Bit
Bit Name
Default
Access
Bit Description
7:0
GPIO masked
interrupt status
register
00000000
R
Masked value of interrupt due to corresponding pin.
0: PrimeCell GPIO line interrupt not active.
1: PrimeCell GPIO line asserting interrupt.
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