AS3525-A/-B C22O22
Data Sheet, Confidential
GPIO interrupt event register
Table 33 GPIO interrupt event register
Name
Base
Default
GPIO1_IEV
GPIO2_IEV
GPIO3_IEV
GPIO4_IEV
AS3525_GPIO1_BASE
AS3525_GPIO2_BASE
AS3525_GPIO3_BASE
AS3525_GPIO4_BASE
0xC80B0000
0xC80C0000
0xC80D0000
0xC80E0000
GPIO interrupt event register
Bits set to HIGH configure the corresponding pin to detect rising edges or high levels,
depending on the corresponding bit value in GPIO interrupt sense register (GPIO1_IS,
…). Clearing a bit configures the pin to detect falling edges or low levels, depending
on the corresponding bit value in GPIO interrupt sense register (GPIO1_IS, …). All bits
are cleared by a reset.
Offset: 0x40C
Bit
Bit Name
Default
Access
Bit Description
7:0
GPIO interrupt event 00000000 RW
register
0: falling edges, or low levels on corresponding pin trigger
interrupts.
1: rising edges, or high levels on corresponding pin trigger
interrupts.
GPIO interrupt mask register
Table 34 GPIO interrupt mask register
Name
Base
Default
GPIO1_IE
GPIO2_IE
GPIO3_IE
GPIO4_IE
AS3525_GPIO1_BASE
AS3525_GPIO2_BASE
AS3525_GPIO3_BASE
AS3525_GPIO4_BASE
0xC80B0000
0xC80C0000
0xC80D0000
0xC80E0000
GPIO interrupt mask register
Bits set to HIGH allow the corresponding pins to trigger their individual interrupts and
the combined GPIOINTR line. Clearing a bit disables interrupt triggering on that pin. All
bits are cleared by a reset.
Offset: 0x410
Bit
Bit Name
Default
Access
Bit Description
7:0
GPIO interrupt mask
register
00000000 RW
0: corresponding pin interrupt is masked.
1: corresponding pin interrupt is not masked.
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