A49FL004
Table 2: FWH Read Cycle
Clock
Field
FWH[3:0]
Direction
Descriptions
Cycle
Start of Cycle: “1101b” to indicate the start of a memory read
cycle. FWH4 must be active (low) for the part to respond. Only the
last start field (before FWH4 transition high) should be recognized.
The start field contents indicate and FWH read cycle.
1
START
1101
IN
ID Select Cycle: Indicates which FWH device should respond. If
the IDSEL field matches the value set on ID[3:0] pins, then the
particular FWH device will respond to subsequent commands.
2
IDSEL
IMADDR
IMSIZE
0000 to 1111
YYYY
IN
IN
Address Cycle: This is the 28-bit memory address. The addressed
transfer most-significant nibble first and least-significant nibble
last. (i.e., a27-24 on FWH[3:0] first, and A3-A0 on FWH[3:0] last).
3-9
10
Memory Size Cycle: Indicates how many bytes will be or
transferred during multi-byte operations. The A49FL004 only
support “0000b” for one byte operation.
0000
1111
IN
IN
Turn-Around cycle 0: The master (Intel ICH) has driven the bus to
then Float all”1”s and then float the bus.
11
12
13
TAR0
TAR1
1111
(Float)
Float
Turn-Around cycle 1: The device takes control of the bus during
then OUT this cycle.
0000
(READY)
Ready Sync: The FWH device indicates the least-significant nibble
of data byte will be ready in next clock cycle.
RSYNC
OUT
Data Cycles: The 8-bits data transferred with least-significant
nibble first and most-significant nibble last. (i.e., I/O3 – I/O0 on
FWH[3:0] first, then I/O7 – I/O4 on FWH[3:0] last).
14-15
DATA
YYYY
1111
OUT
OUT
Turn-Around cycle 0: The FWH device has driven the bus to all
then Float “1”s and then float the bus.
16
17
TAR0
TAR1
1111
(Float)
Float
then IN
Turn-Around cycle 1: The master (Intel ICH) resumes control of
the bus during this cycle.
Figure 4: FWH Memory Read Cycle Waveforms
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
FWH4
START
IDSEL
IMADDR
IMSIZE
TAR0
TAR1
RSYNC
DATA
TAR0
TAR1
FWH[3:0]
PRELIMINARY
(September, 2005, Version 0.0)
7
AMIC Technology, Corp.
AMICC [ AMIC TECHNOLOGY ]
