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ELANSC400-66AC 参数 Datasheet PDF下载

ELANSC400-66AC图片预览
型号: ELANSC400-66AC
PDF下载: 下载PDF文件 查看货源
内容描述: 单芯片,低功耗, PC / AT兼容的微控制器 [Single-Chip, Low-Power, PC/AT-Compatible Microcontrollers]
分类和应用: 微控制器PC
文件页数/大小: 132 页 / 2249 K
品牌: AMD [ AMD ]
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For an even cleaner circuit, the designer could option-  
ally place an analog VCC power plane directly under the  
loop filter circuit.  
32-kHz Crystal Oscillator  
The 32-kHz oscillator circuit is shown in Figure 6; the  
only external component required for operation is a  
32.768-kHz crystal. The inverting amplifier (AMP) is in-  
tegrated on-chip together with the feedback resistor  
and the load capacitors. As shown in Figure 7, the on-  
chip oscillator circuit can be bypassed by removing the  
external crystal, grounding the 32KXTAL1 pin, and  
driving the 32KXTAL2 pin with an external 32-kHz  
clock. (The 32KXTAL2 pin should not exceed 2.0 V.)  
When 32KXTAL1 is grounded, the amplifier no longer  
affects the circuit.  
The value of the loop filter parameters can also affect  
the performance of the filter. For example, the values of  
C1 and R affect lock time and jitter (increasing RC in-  
creases lock time and decreases jitter). The value of  
C2 can help clean up high-frequency noise. Note that  
using too large of values for the components can cause  
the PLL to become unstable. The loop filter component  
value specifications are shown in Table 28 on page 84.  
Intermediate and Low-Speed PLLs  
Figure 8 on page 80 shows the block diagram for both  
the Intermediate and Low-Speed PLLs. Each consists  
of a phase detector, a charge pump, a voltage con-  
trolled oscillator (VCO), an external loop filter, and a  
feedback divider. This is a generic implementation of  
the charge-pump PLL architecture; all four PLLs use  
the same architecture. The Intermediate and Low-  
Speed PLLs differ only in component values and fre-  
quency of operation.  
AMP  
Internal  
External  
The phase detector compares the phase and fre-  
quency of the two clock signals, reference frequency  
(Fr) and feedback frequency (Ff). The Up signal is a  
logic 1 if Fr leads Ff, while the Down signal is a logic 1  
if Ff leads Fr. The Up and Down signals control the  
charge pump. The charge pump either charges or dis-  
charges the loop filter capacitors to change the VCO  
input voltage level. Because the VCO output frequency  
tracks the VCO input voltage, the VCO output fre-  
quency is adjusted whenever Fr and Ff differ in phase  
or frequency.  
32KXTAL1  
32KXTAL2  
32.768-kHz Crystal  
Figure 6. 32-kHz Crystal Circuit  
32KXTAL1  
32 kHz  
Oscillator  
Pin #Y4 2 V  
max  
32KXTAL2  
The feedback divide ratio determines the frequency  
multiplication factor.  
Frequency multiplication is 1/(Feedback Divider).  
Figure 7. 32-kHz Oscillator Circuit  
For the Intermediate PLL, the feedback divider is 1/45;  
therefore, the frequency multiplication is 45. With an  
input frequency of 32.768 kHz, the output frequency is  
1.47456 MHz.  
Loop Filters  
Each of the PLLs in the ÉlanSC400 and ÉlanSC410 mi-  
crocontrollers requires an external loop filter. For a  
cleaner circuit, the designer should consider the following:  
The input clock for the Low-Speed PLL, Fr, originates  
at the Intermediate PLL output. Fr is multiplied by 25 to  
generate the 36.864-MHz clock output.  
Place the loop filter components as close as  
possible to the loop filter signals (LF_INT, LF_LS,  
LF_HS, and LF_VID (ÉlanSC400 microcontroller  
only)), which are located in one corner of the  
microcontroller.  
Route the loop filter signals first and by hand.  
Keep all clocks and noisy signals away from the  
loop filter area (even on the inner layers).  
Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet  
79