CLOCKING
Clock Generation
The ÉlanSC400 and ÉlanSC410 microcontrollers re-
quire only one 32.768-kHz crystal to generate all the
other clock frequencies required by the system. The
output of the on-chip crystal oscillator circuit is used to
generate the various frequencies by utilizing four
Phase-Locked Loop (PLL) circuits. The PLL clock dis-
tribution scheme is shown in Figure 4. Table 26 shows
all the PLL output frequencies and their usage. (Note
that these four PLL circuits are in addition to the inter-
nal CPU PLL and do not replace it.)
load capacitors and the feedback resistor are inte-
grated on-chip.
The four PLLs are called Intermediate PLL, Low-Speed
PLL, High-Speed PLL, and Graphics Dot Clock PLL.
Each of the integrated phase-locked loops has a dedi-
cated pin to support the required external loop filter.
These pins are: LF_INT (Intermediate PLL), LF_LS
(Low-Speed PLL), LF_HS (High-Speed PLL), and
LF_VID (Graphics Dot Clock PLL). (The LF_VID pin is
not supported on the ÉlanSC410 microcontroller.) Two
capacitors and one resistor are required to implement
each loop filter.
The crystal oscillator needs two pins, but it does not re-
quire any external components except the crystal; the
32.768-kHz
Crystal
32.768 kHz
Real-Time
Clock
Oscillator
PMU
1.47456 MHz
DRAM
Controller
Intermediate
PLL
36.864 MHz
UART
Low-Speed
PLL
Timer
20.736–
36.864 MHz
Graphics
Dot Clock
PLL
Graphics
Controller
66.3552 MHz
DRAM
Controller
High-Speed
PLL
ISA Bus
DMA
Controller
CPU and
VL-Bus
Controller
ROM/Flash
Interface
PC Card
Controller
Notes:
On the ÉlanSC400 microcontroller, the graphics controller’s DRAM interface is clocked by the 66-MHz DRAM clock.
Both the ROM/Flash memory interface and the PC Card controller are clocked from the CPU clock. They also have the option
to be run from the slow system clock.
Neither the graphics controller nor the PC Card controller are supported on the ÉlanSC410 microcontroller.
Figure 4. Clock Generation Block Diagram
76
Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet
AMD [ AMD ]
