VCCA
Fr
Up
Loop Filter
36.864 MHz
/16
Charge
Pump
Phase
Detector
Down
C1
R
Ff
C2
PLLRATIO[2–0]
Programmable
Fo
20.736–
36.864 MHz
Vc
VCO
Divider
(9–16)
External
Internal
Figure 9. Graphics Dot Clock PLL Block Diagram
High-Speed PLL
RTC Voltage Monitor
The High-Speed PLL generates a 66.3552-MHz clock
for the DRAM controller. Figure 10 on page 82 shows
the block diagram for the High-Speed PLL. The input to
the High-Speed PLL is the output of the Low-Speed
PLL divided by five. The feedback divider is nine, which
results in an output frequency (Fo) of 66.3552 MHz.
This frequency is divided by 2 in the PMU to provide the
33-MHz input for the PLL in the CPU core.
The voltage monitor for the RTC block is shown in
Figure 11 on page 82. Its functions are to provide a
reset signal to the RTC block when it detects a low
backup battery voltage, and to provide an early warn-
ing signal when the system is powering down.
The internal RTC reset signal is asserted on power-up
if the back-up battery voltage drops below 2.4 V. The
one shot prevents multiple resets during power-on.
Band Gap Block
An internal power-down signal is used by the RTC to
isolate the RTC core from the rest of the
microcontroller. The RTC voltage monitor uses the
RESET assertion to detect a power-down. For proper
operation, RESET and VCC must follow the timing in
Figure 12 on page 83.
The band gap reference circuit generates the bias cur-
rents for the four PLLs and provides a 2.4-V reference
source for the RTC voltage monitor. The current
sources, constant over VCC, temperature, and process
variations, are used by the four PLL charge pumps for
adjusting the PLL operating frequency. The 2.4-V refer-
ence voltage is used by the RTC voltage monitor to de-
tect a low backup battery voltage level.
Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet
81
AMD [ AMD ]
