RESET
3.3 V
2.7 V
VCC
33 µs
(min)
32 kHz
Notes:
1. These timings apply only when powering down the chip while leaving only the RTC powered.
2. Applies to all VCC except for the VCC_RTC, which is left on for this mode.
3. Guarantees at least one rising edge after reset before 2.7 volts is reached.
Figure 12. Timing Diagram for RTC-On Power-Down Sequence
Programmable Interval Timer (PIT)
Clock Specifications
The ÉlanSC400 and ÉlanSC410 microcontrollers are
The specifications for the external components re-
quired to implement the four PLL loop filters are shown
in Table 28 on page 84.
equipped with a Programmable Interval Timer (PIT)
that is software-compatible with PC/AT 8254 system
timers. Historically, the clock source for this timer has
been 1.19318 MHz. However, the internal PIT clock
source is 1.1892 MHz. The user has two options:
Table 29 on page 84 lists the electrical specifications
for the analog VCC (VCCA) pin.
The on-chip crystal oscillator circuit supports most
generic 32.768-kHz crystals as long as the
specification for the crystals meet the electrical
parameters listed in Table 30 on page 84.
■ Use the internal PIT clock source (1.1892 MHz),
which can adversely affect the Legacy software that
depends on the 1.19318-MHz frequency.
■ Drive an external 1.19318-MHz clock onto the
CLK_IO pin and program this signal to be the
source of the PIT clock.
The worst-case start-up time required for the PLLs is
shown in Table 31 on page 84.
The PLL jitter specification is listed in Table 32 on
page 85.
For more details on this feature, refer to the subsection
on configuring Timer Channel 0 in the programmable
interval timer section of the ÉlanSC400 and
ÉlanSC410 Microcontrollers User’s Manual, order
#21030.
Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet
83
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