Integrated Peripheral Clock Sources
Table 26 and Figure 5 show the primary peripheral
clocks internal to the microcontroller and the PLL and
divider sources that are used in the generation of these
clocks. Note that several of the peripheral clocks are
programmable. This programmability is either directly
controlled by system firmware or is forced due to a
power-management mode change. The graphics con-
troller and the PC Card controller are not supported on
the ÉlanSC410 microcontroller.
Table 26. Integrated Peripheral Clock Sources
Source PLL
Divider
Resulting Frequency
Where Used
Intermediate PLL
1.4746 MHz
1
1.4746 MHz
Low-speed PLL input
Low-speed PLL
36.864 MHz
1
36.864 MHz
High-speed PLL input
Graphics dot clock PLL input
20
1.8432 MHz
18.4328 MHz
1.1892 MHz
UART
2
UART
31
PIT
Graphics dot clock PLL
36.864 MHz
Programmable
20.736–36.864 MHz
36.864 MHz
Graphics controller dot clock
Graphics controller
1
1
High-speed PLL
66.3552 MHz
66.3552 MHz
DRAM controller
Graphics controller
2
4
33.1776 MHz
16.5888 MHz
CPU
VL-bus controller
CPU
VL-bus controller
DMA controller
8
8.2944 MHz
4.1472 MHz
2.0736 MHz
1.0368 MHz
CPU
VL-bus controller
ISA bus controller
ROM/Flash memory interface
DMA controller
PC Card controller
16
32
64
CPU
VL-bus controller
ISA bus controller
ROM/Flash memory interface
DMA controller
PC Card controller
CPU
VL-bus controller
ISA bus controller
ROM/Flash memory interface
DMA controller
PC Card controller
CPU
VL-bus controller
ISA bus controller
ROM/Flash memory interface
DMA controller
PC Card controller
Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet
77
AMD [ AMD ]
