VCCA
Loop
Up
Filter
Reference
Frequency
Phase
Charge
Pump
Detector
(Fr)
Down
C1
Feedback
Frequency
R
C2
(Ff)
Vc
VCO
Divider
External
Internal
Frequency Output (Fo)
Figure 8. Intermediate and Low-Speed PLLs Block Diagram
Graphics Dot Clock PLL (ÉlanSC400 Microcontroller Only)
The input clock to the Graphics Dot Clock PLL is the
output clock (36.864 MHz) of the Low-Speed PLL di-
vided by 16. The Graphics Dot Clock PLL is not sup-
ported on the ÉlanSC410 microcontroller. The output
frequency is programmable using three extended reg-
ister bits (PLLRATIO[2–0]) in the range of 20.736 MHz
to 36.864 MHz (spaced 2.304 MHz apart). These three
bits (in graphics index register 4Ch) control the output
frequency by selecting the divide value in the feedback
divider as shown in Table 27.
The Graphics Dot Clock PLL requires a stabilization
period after changing frequency. Figure 9 shows the
block diagram for the Graphics Dot Clock PLL.
Table 27. Frequency Selection Control for
Graphics Dot Clock PLL
Output Frequency
PLLRATIO[2–0]
Divider
(MHz)
20.736
23.04
000
001
010
011
100
101
110
111
9
10
11
12
13
14
15
16
25.344
27.648
29.952
32.256
34.56
36.864
80
Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet
AMD [ AMD ]
