CFG3 Pin
This configuration pin is used for selecting between the
GPIO_CS4–GPIO_CS2 I/O pins and the SD bus buffer
control signals: DBUFOE, DBUFRDL, and DBUFRDH.
When the buffer control signal configuration is selected
using the CFG3 pin, the DBUFOE, DBUFRDL, and
DBUFRDH signals are driven from boot time on for all
accesses to the peripheral data bus. These signals are
used for the external system bus transceiver control.
See Table 24 for the CFG3 configuration definitions.
Table 24. CFG3 Configuration
CFG3
Configuration
0
Enables the GPIO_CS4–GPIO_CS2 signals
on the I/O pins
1
Enables the SD bus buffer control signals
DBUFOE, DBUFRDL, and DBUFRDH
on the I/O pins
BNDSCN_EN Pin
The BNDSCN_EN configuration pin (see Table 25) is
used to enable the boundary scan function I/O pins.
The following pins are configured for their boundary
scan function when BNDSCN_EN is asserted:
■ BNDSCN_TCK
■ BNDSCN_TMS
■ BNDSCN_TDI
■ BNDSCN_TDO
Table 25. BNDSCN_EN Configuration
BNDSCN_EN Configuration
0
1
Enables the PC Card function
Enables the boundary scan functions:
BNDSCN_TCK, BNDSCN_TMS,
BNDSCN_TDI, and BNDSCN_TDO
Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet
75
AMD [ AMD ]
