Table 22. CFG0 and CFG1 Configuration
Using the Configuration Pins to Select
Pin Functions
CFG1
CFG0
Configuration
The configuration pins are used only for those func-
tions that must be selected at reset, prior to firmware
execution. All other I/O functions are selected using
configuration registers.
0
0
1
1
0
1
0
1
x8 ROMCS0 ROM interface
Reserved
x16 ROMCS0 ROM interface
x32 ROMCS0 ROM interface
Table 21 provides an overview of the configuration pin
functions. All of the CFG pins have weak internal pull-
down resistors that select the default function. External
pullup resistors are required to select an alternative
function.
CFG2 Pin—ÉlanSC400 Microcontroller Only
This configuration pin (see Table 23) is used on the
ÉlanSC400 microcontroller to select the ROMCS0
steering at system boot time. The boot ROM chip se-
lect (ROMCS0) can either be enabled to drive the
ROMCS0 pin or can be rerouted to drive the PC Card
(Socket A only) interface chip selects. The CFG0 and
CFG1 pins are still used to select the data bus width for
the ROMCS0 decode, regardless of the CFG2 config-
uration. The PC Card ROMCS0 redirection should not
be selected when the CFG0 and CFG1 configuration
pins are set to select a x32 ROM interface.
Table 21. Pinstrap Bus Buffer Options
ROMCS0 DBUFOE
CFG3
CFG1 CFG0
Data
Width
DBUFRDL R32BFOE
DBUFRDH
(1)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
x8
Disabled
Disabled
Reserved Reserved Reserved
x16
x322
x8
Disabled
Disabled
Enabled
Disabled
Enabled
Disabled
When the ROM chip select decode has been redi-
rected to PC Card Socket A, all of the normal PC Card
controller features can still be used to drive the PC
Card Socket A interface. The ROM chip select decode
remapping to the PC Card socket can be enabled and
disabled using firmware at any time.
Reserved Reserved Reserved
x16
x322
Enabled
Enabled
Disabled
Enabled
Notes:
Table 23. CFG2 Configuration (ÉlanSC400
microcontroller only)
1. CFG3 is defined as the enable/disable for the DBUFOE,
DBUFRDL, and DBUFRDH signals. They can be enabled
independently of whether a x32 D bus is selected via the
firmware to support the VL local bus or x32 DRAM interface.
CFG2
Configuration
0
Enables the ROMCS0 decode
on the ROMCS0 pin
2. The x32 ROM option must be selected for ROMCS0 for
the R32BFOE signal to be enabled. The selection of the
DBUFOE, DBUFRDL, and DBUFRDH signals are still
dependent only on the CFG3 signal.
1
Enables the ROMCS0 decode
to access PC Card Socket A
CFG0 and CFG1 Pins
These pins (shown in Table 22) configure the data bus
width (x8, x16, or x32) of the ROM interface that is se-
lected by the ROMCS0 pin. If a x32 ROM is selected,
these pins also enable the ROM x32 Data Bus Buffer
Output Enable signal (R32BFOE). If a 32-bit data bus
width is selected for the ROM interface, the R32BFOE
signal will be asserted for all ROMCSx accesses to
32-bit ROM. Exercise caution because the data bus
width for the ROMCS0 interface can also be changed
through programming. This feature was implemented
mainly for testing.
.
74
Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet
AMD [ AMD ]
