RST
CLK
GNT
REQ
AD[31:0]
C/BE[3:0]
IDSEL
FRAME
IRDY
FFFFFFFF
0000FFFF
3
1
F
7
TRDY
DEVSEL
STOP
PERR
SERR
PAR
...
INTA
...
...
22206B-53
Figure 49. NAND Tree Waveform
10h) must be performed to set the device into 32-bit
I/O mode.
Reset
There are four different types of RESET operations that
may be performed on the Am79C978 device,
H_RESET, S_RESET, STOP, and POR. The following
is a description of each type of RESET operation.
S_RESET
Software Reset (S_RESET) is an Am79C978 reset op-
eration that has been created by a read access to the
Reset register, which is located at offset 14h in Word
I/O mode or offset 18h in DWord I/O mode from the
Am79C978 I/O or memory mapped I/O base address.
H_RESET
Hardware Reset (H_RESET) is an Am79C978 reset
operation that has been created by the proper asser-
tion of the RST pin of the Am79C978 device while the
PG pin is HIGH. When the minimum pulse width timing
as specified in the RST pin description has been satis-
fied, an internal reset operation will be performed.
S_RESET will reset all of or some portions of CSR0, 3,
4, 15, 80, 100, and 124 to default values. For the iden-
tity of individual CSRs and bit locations that are af-
fected by S_RESET, see the individual CSR register
descriptions. S_RESET will not affect any PCI configu-
ration space location. S_RESET will not affect any of
the BCR register values. S_RESET will cause the mi-
crocode program to jump to its reset state. Following
the end of the S_RESET operation, the controller will
not attempt to read the EEPROM device. After
S_RESET, the host must perform a full re-initialization
of the controller before starting network activity.
S_RESET will cause REQ to deassert immediately.
STOP (CSR0, bit 2) or SPND (CSR5, bit 0) can be
used to terminate any pending bus mastership request
in an orderly sequence.
H_RESET will program most of the CSR and BCR reg-
isters to their default value. Note that there are several
CSR and BCR registers that are undefined after
H_RESET. See the sections on the individual registers
for details.
H_RESET will clear most of the registers in the PCI
configuration space. H_RESET will cause the micro-
code program to jump to its reset state. Following the
end of the H_RESET operation, the controller will at-
tempt to read the EEPROM device through the EE-
PROM interface.
H_RESET will clear DWIO (BCR18, bit 7) and the con-
troller will be in 16-bit I/O mode after the reset opera-
tion. A DWord write operation to the RDP (I/O offset
S_RESET terminates all network activity abruptly. The
host can use the suspend mode (SPND, CSR5, bit 0)
to terminate all network activity in an orderly sequence
before issuing an S_RESET.
94
Am79C978
AMD [ AMD ]
