TBR0: 10BASE-T PHY Control Register (Register 0)
Table 65. TBR0: 10BASE-T PHY Control Register (Register 0)
Read/Write
(Note 1)
Default
Value
Soft
Reset
Reg
Bits
Name
Soft Reset (Note 2)
Loopback
Description
When write: 1 = PHY software reset,
0 = normal operation.
0
15
R/W, SC
R/W
0
0
0
0
When read: 1 = reset in process,
0 = reset done.
0 = asserts Loopback mode,
1 = deasserts Loopback mode
0
14
Speed Selection
(Note 3)
1 = 100 Mbps,
0 = 10 Mbps
0
0
0
13
12
11
R/W
R/W
R/W
1
1
0
1
1
0
Auto-Negotiation
Enable
1 = enable Auto-Negotiation,
0 = disable Auto-Negotiation
1 = power down,
0 = normal operation
Power Down
Isolate
1 = electrically isolate PHY
0 = normal operation
0
0
10
9
R/W
1
0
1
0
(Note 4)
Restart Auto-
Negotiation
1 = restart Auto-Negotiation,
0 = normal operation
R/W, SC
Retains
previous
value
Duplex Mode
(Note 3)
1 = Full-Duplex,
0 = Half-Duplex
0
0
8
R/W
1
1 = enable COL signal test,
0 = disable COL signal test
7
Collision Test
Reserved
R/W
RO
0
0
0
0
0
6-0
Write as 0, ignore on read
Notes:
1. R/W = Read/Write, SC = Self Clearing, RO = Read only.
2. Soft Reset does not reset the PDX block. Refer to the Soft Reset Section for details.
3. Bits 8 and 13 have no effect if Auto-Negotiation is enabled (Bit 12 = 1).
4. If the ISOL pin of the chip and the Isolate bit in Register 0 is 1, this bit will be set.
Am79C978
189
AMD [ AMD ]
