欢迎访问ic37.com |
会员登录 免费注册
发布采购

AM79C978KC/W 参数 Datasheet PDF下载

AM79C978KC/W图片预览
型号: AM79C978KC/W
PDF下载: 下载PDF文件 查看货源
内容描述: 单芯片1/10 Mbps的PCI家庭网络控制器 [Single-Chip 1/10 Mbps PCI Home Networking Controller]
分类和应用: 控制器PC
文件页数/大小: 261 页 / 3499 K
品牌: AMD [ AMD ]
 浏览型号AM79C978KC/W的Datasheet PDF文件第171页浏览型号AM79C978KC/W的Datasheet PDF文件第172页浏览型号AM79C978KC/W的Datasheet PDF文件第173页浏览型号AM79C978KC/W的Datasheet PDF文件第174页浏览型号AM79C978KC/W的Datasheet PDF文件第176页浏览型号AM79C978KC/W的Datasheet PDF文件第177页浏览型号AM79C978KC/W的Datasheet PDF文件第178页浏览型号AM79C978KC/W的Datasheet PDF文件第179页  
of the PCI configuration space,  
bits 7-0). Refer to the description  
of DATA register for the meaning  
of this field.  
unaffected by S_RESET and the  
STOP bit.  
6-0 PMR_ADDR Pattern Match Ram Address.  
These bits are the Pattern Match  
Ram address to be written to or  
read from.  
These bits are always read ac-  
cessible. DATA7 is read only.  
Cleared by H_RESET and is not  
affected by S_RESET or setting  
the STOP bit.  
These bits are read and write ac-  
cessible always. PMR_ADDR is  
reset to 0 after H_RESET, and is  
unaffected by S_RESET and the  
STOP bit.  
BCR45: OnNow Pattern Matching Register 1  
Note: This register is used to control and indirectly ac-  
cess the Pattern Match RAM (PMR). When BCR45 is  
written and the PMAT_MODE bit (bit 7) is 1, Pattern  
Match logic is enabled. No bus accesses into PMR are  
possible, and BCR46, BCR47, and all other bits in  
BCR45 are ignored. When PMAT_MODE is set, a read  
of BCR45, BCR46, or BCR47 returns all undefined bits  
except for PMAT_MODE.  
BCR46: OnNow Pattern Matching Register 2  
Note: This register is used to control and indirectly ac-  
cess the Pattern Match RAM (PMR). When BCR45 is  
written and the PMAT_MODE bit (bit 7) is 1, Pattern  
Match logic is enabled. No bus accesses into PMR are  
possible, and BCR46, BCR47, and all other bits in  
BCR45 are ignored. When PMAT_MODE is set, a read  
of BCR45, BCR46, or BCR47 returns all undefined bits  
except for PMAT_MODE.  
When BCR45 is written and the PMAT_MODE bit is 0,  
the Pattern Match logic is disabled and accesses to the  
PMR are possible. Bits 6-0 of BCR45 specify the ad-  
dress of the PMR word to be accessed. Following the  
write to BCR45, the PMR word may be read by reading  
BCR45, BCR46 and BCR47 in any order. To write to  
PMR word, the write to BCR45 must be followed by a  
write to BCR46 and a write to BCR47 in that order to  
complete the operation. The RAM will not actually be  
written until the write to BCR47 is complete. The write  
to BCR47 causes all 5 bytes (four bytes of BCR46-47  
and the upper byte of the BCR45) to be written to what-  
ever PMR word is addressed by bits 6:0 of BCR45.  
When BCR45 is written and the PMAT_MODE bit is 0,  
the Pattern Match logic is disabled and accesses to the  
PMR are possible. Bits 6-0 of BCR45 specify the ad-  
dress of the PMR word to be accessed. Following the  
write to BCR45, the PMR word may be read by reading  
BCR45, BCR46 and BCR47 in any order. To write to  
PMR word, the write to BCR45 must be followed by a  
write to BCR46 and a write to BCR47 in that order to  
complete the operation. The RAM will not actually be  
written until the write to BCR47 is complete. The write  
to BCR47 causes all 5 bytes (four bytes of BCR46-47  
and the upper byte of the BCR45) to be written to what-  
ever PMR word is addressed by bits 6:0 of BCR45.  
Bit  
Name  
Description  
31-16 RES  
Reserved locations. Written as  
zeros and read as undefined.  
Bit  
Name  
Description  
15-8 PMR_B0  
Pattern Match RAM Byte 0. This  
byte is written into or read from  
Byte 0 of the Pattern Match RAM.  
31-16 RES  
Reserved locations. Written as  
zeros and read as undefined.  
15-8 PMR_B2  
Pattern Match RAM Byte 2. This  
byte is written into or read from  
Byte 2 of the Pattern Match RAM.  
These bits are read and write ac-  
cessible always. PMR_B0 is un-  
defined after H_RESET, and is  
unaffected by S_RESET and the  
STOP bit.  
These bits are read and write ac-  
cessible always. PMR_B2 is un-  
defined after H_RESET, and is  
unaffected by S_RESET and the  
STOP bit.  
7 PMAT_MODE  
Pattern Match Mode. Writing a 1  
to this bit will enable Pattern  
Match Mode and should only be  
done after the Pattern Match  
RAM has been programmed.  
7-0  
PMR_B1  
Pattern Match RAM Byte 1. This  
byte is written into or read from  
Byte 1 of Pattern Match RAM.  
These bits are read and write ac-  
cessible always. PMAT_MODE is  
reset to 0 after H_RESET, and is  
These bits are read and write ac-  
cessible always. PMR_B1 is un-  
Am79C978  
175