9-8
D2_SCALE These bits correspond to the
DATA_SCALE field of the
PMCSR (offset Register 44 of the
PCI configuration space, bits 14-
13). Refer to the description of
DATA_SCALE for the meaning of
this field.
7-0
DATA3
These bits correspond to the PCI
DATA register (offset Register 47
of the PCI configuration space,
bits 7-0). Refer to the description
of DATA register for the meaning
of this field.
These bits are always read ac-
cessible. DATA3 is read only.
Cleared by H_RESET and is not
affected by S_RESET or setting
the STOP bit.
These bits are always read ac-
cessible. D2_SCALE is read only.
Cleared by H_RESET and is not
affected by S_RESET or setting
the STOP bit.
BCR41: PCI DATA Register 4 (DATA4) Alias
Register
7-0
DATA2
These bits correspond to the PCI
DATA register (offset Register 47
of the PCI configuration space,
bits 7-0). Refer to the description
of DATA register for the meaning
of this field.
Note: This register is an alias of the DATA register and
also of the DATA_SCALE field of the PCMCR register.
Since these two are read only, BCR41 provides a
means of programming them through the EEPROM.
The contents of this register are copied into the corre-
sponding fields pointed with the DATA_SEL field set to
four. Bits 15-0 in this register are programmable
through the EEPROM.
These bits are always read ac-
cessible. DATA2 is read only.
Cleared by H_RESET and is not
affected by S_RESET or setting
the STOP bit.
Bit
Name
Description
BCR40: PCI DATA Register 3 (DATA3) Alias
Register
15-10 RES
Reserved locations. Written as
zeros and read as undefined.
Note: This register is an alias of the DATA register and
also of the DATA_SCALE field of the PCMCR register.
Since these two are read only, BCR40 provides a
means of programming them through the EEPROM.
The contents of this register are copied into the corre-
sponding fields pointed with the DATA_SEL field set to
three. Bits 15-0 in this register are programmable
through the EEPROM.
9-8
D4_SCALE These bits correspond to the
DATA_SCALE field of the PMC-
SR (offset register 44 of the PCI
configuration space, bits 14-13).
Refer to the description of
DATA_SCALE for the meaning of
this field.
Bit
Name
Description
Read
accessible
always.
D4_SCALE is read only. Cleared
by H_RESET and is not affected
by S_RESET or setting the STOP
bit
15-10 RES
Reserved locations. Written as
zeros and read as undefined.
9-8
D3_SCALE These bits correspond to the
DATA_SCALE field of the PMC-
SR (offset Register 44 of the PCI
configuration space, bits 14-13).
Refer to the description of
DATA_SCALE for the meaning of
this field.
7-0
DATA4
These bits correspond to the PCI
DATA register (offset Register 47
of the PCI configuration space,
bits 7-0). Refer to the description
of DATA register for the meaning
of this field.
These bits are always read ac-
cessible. D3_SCALE is read only.
Cleared by H_RESET and is not
affected by S_RESET or setting
the STOP bit.
Read accessible always. DATA4
is read only. Cleared by
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
Am79C978
173
AMD [ AMD ]
