LINT[16] is implied to be a 1, so
RXPOLLINT[15] is significant
and does not represent the sign
of the two’s complement RXPOL-
LINT value.)
10
APERREN Advanced Parity Error Handling
Enable. When APERREN is set
to 1, the BPE bits (RMD1 and
TMD1, bit 23) start having a
meaning. BPE will be set in the
descriptor associated with the
buffer that was accessed when a
data parity error occurred. Note
that since the advanced parity er-
ror handling uses an additional bit
in the descriptor, SWSTYLE (bits
7-0 of this register) must be set to
2 or 3 to program the Am79C978
controller to use 32-bit software
structures.
The default value of this register
is 0000h. This corresponds to a
polling interval of 65,536 clock
periods
(1.966
ms
when
CLK = 33 MHz). The RXPOL-
LINT value of 0000h is created
during the microcode initialization
routine and, therefore, might not
be seen when reading CSR49 af-
ter H_RESET or S_RESET.
APERREN does not affect the re-
porting of address parity errors or
data parity errors that occur when
the Am79C978 controller is the
target of the transfer.
If the user desires to program a
value for RXPOLLINT other than
the default, then the correct pro-
cedure is to first set INIT only in
CSR0. Then, when the initializa-
tion sequence is complete, the
user must set STOP (CSR0, bit
2). Then the user may write to
CSR49 and set STRT in CSR0.
In this way, the default value of
0000h in CSR47 will be overwrit-
ten with the desired user value.
Read anytime, write accessible
only when either the STOP or the
SPND bit is set. APERREN is
cleared by H_RESET and is not
affected by S_RESET or STOP.
9
8
RES
Reserved location. Written as
zero and read as undefined.
If the user does not use the stan-
dard initialization procedure
(standard implies use of an initial-
ization block in memory and set-
ting the INIT bit of CSR0), but
instead chooses to write directly
to each of the registers that are
involved in the INIT operation, it
is imperative that the user also
writes all zeros to CSR49 as part
of the alternative initialization se-
quence.
SSIZE32
Software Size 32 bits. When set,
this bit indicates that the
Am79C978 controller utilizes 32-
bit software structures for the ini-
tialization block and the transmit
and receive descriptor entries.
When cleared, this bit indicates
that the Am79C978 controller uti-
lizes 16-bit software structures for
the initialization block and the
transmit and receive descriptor
entries. In this mode, the
Am79C978 controller is back-
wards compatible with the
Am7990 LANCE and Am79C960
PCnet-ISA controllers.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
The value of SSIZE32 is deter-
mined by the Am79C978 control-
ler according to the setting of the
Software Style (SWSTYLE, bits
7-0 of this register).
CSR58: Software Style
Thisregisterisanaliasofthelocation BCR20. Accesses
to and from this register are equivalent to accesses to
BCR20.
Read
accessible
always.
Bit
Name
Description
SSIZE32 is read only; write oper-
ations will be ignored. SSIZE32
will be cleared after H_RESET
(since SWSTYLE defaults to 0)
31-11 RES
Reserved locations. Written as
zeros and read as undefined.
134
Am79C978
AMD [ AMD ]
